1999 Sep 16

8

Philips Semiconductors

Objective specification

Dual 8-bit, 100 Msps A/D converter with

DPGA

TDA8798

Table 1

Serial interface truth table; see notes 1 and 2

Notes

1. ‘

← Di’: shifting LSB and loading new LSB with value Di.

2. In count-up/count-down mode, the gain control register cannot be incremented above the maximum gain value of 63,

or decremented below the minimum gain value of 0.

SMODE

SCLK

SEN1

SEN2

SDATA

ACTION

0

1

1

U

WAIT

0

1

1

Di

SISR: SISR

← Di

0

0

1

1

SISR: SISR

← 1

GCR1: GCR1 + 1

0

0

1

0

SISR: SISR

← 0

GCR1: GCR1

− 1

0

1

0

1

SISR: SISR

← 1

GCR2: GCR2 + 1

0

1

0

0

SISR: SISR

← 0

GCR2: GCR2

− 1

0

0

0

1

SISR: SISR

← 1

GCR1: GCR1 + 1

GCR2: GCR2 + 1

0

0

0

0

SISR: SISR

← 0

GCR1: GCR1

− 1

GCR2: GCR2

− 1

1

U

WAIT

1

Di

SISR: SISR

← Di

1

U

GCR1: SISR

1

U

GCR2: SISR

1

U

GCR1: SISR

GCR2: SISR

X,

X,

X,

X,

X,

X,

X,

X,

X,

X,

X,