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DS3101 Datasheet(PDF) 8 Page - Dallas Semiconductor |
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DS3101 Datasheet(HTML) 8 Page - Dallas Semiconductor |
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8 / 149 page  DS3101 Stratum 3/3E Timing Card IC 8 of 149 3. APPLICATION EXAMPLE Figure 3-1. Typical Application Example DS3100 to BITS/SSU TCXO or OCXO Monitor, Divider, Selector T4 DPLL T4 APLL BITS Tx BITS Tx T0 DPLL Monitor, Divider, Selector BITS Rx BITS Rx micro controller Timing Card (1 of 2) Backplane DS1, E1 or 2048 kHz DS1, E1 or 2048 kHz from BITS/SSU Timing Card (2 of 2) Identical to Timing Card 1 T0 APLL Line Card (1 of N) Line Card (N of N) <N> <N> <N> <N> <1> <1> <1> <1> N typically 19.44 MHz point-to-point or multidrop buses create derived DS1 or E1/2048 kHz clock from 19.44 MHz frequency locked to line clock create DS1/E1 frames, insert SSMs, transmit DS1, E1 or 2048 kHz sync signal activty and frequency monitoring, select highest priority valid input clock/data recovery, equalizer, framer, extract SSMs Stratum 3 or 3E: jitter/wander filtering, hitless switching, phase adjust, holdover divide line clock down to backplane rate, send to timing cards select best system clock, hitless switching, basic holdover DPLL APLL clock multiplication, jitter cleanup to port SERDES N <0> N N <0> 4. DETAILED DESCRIPTION Figure 2-1 illustrates the blocks described in this section and how they relate to one another. Section 5 provides a detailed feature list. The DS3101 is a highly integrated timing card IC for systems with SONET/SDH ports. At the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4 1. DPLL technology makes uses of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. The DS3101’s DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to 155.52MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander. 1 These names are adapted from output ports of the SETS function specified in ITU and ETSI standards such as ETSI EN 300 462-2-1. |
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