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DS3101 Datasheet(PDF) 5 Page - Dallas Semiconductor

Part No. DS3101
Description  Stratum 3/3E Timing Card IC
Download  149 Pages
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Maker  DALLAS [Dallas Semiconductor]
Homepage  http://www.dalsemi.com
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DS3101 Datasheet(HTML) 5 Page - Dallas Semiconductor

 
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DS3101 Stratum 3/3E Timing Card IC
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LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 12
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 13
Table 6-3. Global Pin Descriptions ............................................................................................................................ 14
Table 6-4. Parallel Interface Pin Descriptions ........................................................................................................... 15
Table 6-5. SPI Bus Mode Pin Descriptions ............................................................................................................... 16
Table 6-6. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-7. General-Purpose I/O Pin Descriptions ..................................................................................................... 16
Table 6-8. Power-Supply Pin Descriptions ................................................................................................................ 17
Table 7-1. GR-1244 Stratum 3E/3 Stability Requirements........................................................................................ 19
Table 7-2. Input Clock Capabilities ............................................................................................................................ 21
Table 7-3. Locking Frequency Modes ....................................................................................................................... 22
Table 7-4. Default Input Clock Priorities .................................................................................................................... 25
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32
Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 36
Table 7-7. Output Clock Capabilities ......................................................................................................................... 38
Table 7-8. Digital1 and Digital2 Frequencies............................................................................................................. 41
Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) .............................................................................. 42
Table 7-10. T0 APLL Frequency to T0 Path Configuration ....................................................................................... 42
Table 7-11. T4 APLL Frequency to T4 Path Configuration ....................................................................................... 43
Table 7-12. OC1 to OC7 Output Frequency Selection .............................................................................................. 44
Table 7-13. Possible Frequencies for OC1 to OC7 ................................................................................................... 44
Table 7-14. Equipment Redundancy Methodology ................................................................................................... 48
Table 7-15. Composite Clock Variations ................................................................................................................... 52
Table 7-16. GR-378 Composite Clock Interface Specification .................................................................................. 54
Table 7-17. G.703 Synchronization Interfaces Specification..................................................................................... 54
Table 7-18. Microprocessor Interface Modes ............................................................................................................ 55
Table 8-1. Top-Level Memory Map............................................................................................................................ 59
Table 8-2. Register Map ............................................................................................................................................ 60
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 128
Table 9-2. JTAG ID Code ........................................................................................................................................ 129
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 130
Table 10-2. DC Characteristics................................................................................................................................ 130
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 131
Table 10-4. LVDS Pins ............................................................................................................................................ 131
Table 10-5. LVPECL Pins........................................................................................................................................ 132
Table 10-6. AMI Composite Clock Pins ................................................................................................................... 133
Table 10-7. Recommended External Components for Output Clock OC8.............................................................. 133
Table 10-8. Input Clock Timing................................................................................................................................ 134
Table 10-9. Input Clock to Output Clock Delay ....................................................................................................... 134
Table 10-10. Output Clock Phase Alignment, Frame Sync Alignment Mode......................................................... 134
Table 10-11. Parallel Interface Timing..................................................................................................................... 135
Table 10-12. SPI Interface Timing ........................................................................................................................... 138
Table 10-13. JTAG Interface Timing........................................................................................................................ 139
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 140
Table 13-1. Thermal Properties, Natural Convection .............................................................................................. 146


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