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PIC24HJ12GP201 Datasheet(PDF) 2 Page - Microchip Technology |
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PIC24HJ12GP201 Datasheet(HTML) 2 Page - Microchip Technology |
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2 / 80 page  dsPIC33F/PIC24H PROGRAMMING SPECIFICATION DS70152D-page 2 Preliminary © 2007 Microchip Technology Inc. FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ This specification is divided into major sections that describe the programming methods independently. Section 3.0 “Device Programming – Enhanced ICSP” describes the Enhanced ICSP method. Section 5.0 “Device Programming – ICSP” describes the ICSP method. 2.1 Power Requirements All devices in the dsPIC33F/PIC24H family are dual volt- age supply designs: one supply for the core and another for the peripherals and I/O pins. A regulator is provided on-chip to alleviate the need for two external voltage supplies. All of the dsPIC33F/PIC24H devices power their core digital logic at a nominal 2.5V. To simplify system design, all devices in the dsPIC33F/PIC24H Program- ming Specification family incorporate an on-chip regu- lator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as tantalum) must be connected to the VDDCORE pin (Figure 2-2). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”. FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR 2.2 Program Memory Write/Erase Requirements The program Flash memory on the dsPIC33F/PIC24H has a specific write/erase requirement that must be adhered to for proper device operation. The rule is that any given word in memory must not be written without first erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle. The pro- gramming methods specified in this document comply with this requirement. dsPIC33F/PIC24H Programmer Programming Executive On-Chip Memory Note: A program memory word can be pro- grammed twice before an erase, but only if (a) the same data is used in both pro- gram operations or (b) bits containing ‘1’ are set to ‘0’ but no ‘0’ is set to ‘1’. Note 1: These are typical operating voltages. Refer to Section TABLE 8-1: “AC/DC Charac- teristics and Timing Requirements” for the full operating ranges of VDD and VDD VDDCORE VSS dsPIC33F/PIC24H CF 3.3V |
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