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CDCEL949 Datasheet(PDF) 5 Page - Texas Instruments |
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CDCEL949 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 31 page www.ti.com TIMING REQUIREMENTS DEVICE CHARACTERISTICS CDCE949 CDCEL949 SCAS844 – JUNE 2007 over recommended ranges of supply voltage, load and operating free-air temperature CLK_IN Requirements MIN NOM MAX UNIT PLL Bypass Mode 0 160 f(CLK) LVCMOS clock input frequency MHz PLL Mode 8 160 tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns dutyCLK Duty cycle CLK at VDD / 2 40% 60% STANDARD FAST MODE MODE SDA/SCL TIMING REQUIREMENTS (see Figure 12) UNIT MIN MAX MIN MAX f(SCL) SCL clock frequency 0 100 0 400 kHz tsu(START) START setup time (SCL high before SDA low) 4.7 0.6 μs th(START) START hold time (SCL low after SDA low) 4 0.6 μs tw(SCLL) SCL low-pulse duration 4.7 1.3 μs tw(SCLH) SCL high-pulse duration 4 0.6 μs th(SDA) SDA hold time (SDA valid after SCL low) 0 3.45 0 0.9 μs tsu(SDA) SDA setup time 250 100 ns tr SCL/SDA input rise time 1000 300 ns tf SCL/SDA input fall time 300 300 ns tsu(STOP) STOP setup time 4.0 0.6 μs tBUF Bus free time between a STOP and START condition 4.7 1.3 μs over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETER All PLLs on 38 All outputs off, fCLK = 27 IDD Supply current (see Figure 3) mA MHz, fVCO= 135 MHz; Per PLL 9 CDCE949 4 VDDOUT=3.3 V Supply current (see Figure 4 and No load, all outputs on, IDD(OUT) mA Figure 5) fout = 27 MHz CDCEL949 2 VDDOUT=1.8 V Power down current. Every circuit IDD(PD) fIN = 0 MHz, VDD = 1.9 V 50 μA powered down except SDA/SCL Supply voltage Vdd threshold for power V(PUC) 0.85 1.45 V up control circuit fVCO VCO frequency range of PLL 80 230 MHz fOUT LVCMOS output frequency 230 MHz LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; II = –18 mA –1.2 V II LVCMOS input current VI = 0 V or VDD; VDD = 1.9 V ±5 μA IIH LVCMOS input current for S0/S1/S2 VI = VDD; VDD = 1.9 V 5 μA IIL LVCMOS input current for S0/S1/S2 VI = 0 V; VDD = 1.9 V –4 μA Input capacitance at Xin/Clk VICLK = 0 V or VDD 6 CI Input capacitance at Xout VIXout = 0 V or VDD 2 pF Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 (1) All typical values are at respective nominal VDD. 5 Submit Documentation Feedback |
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