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AD1884 Datasheet(PDF) 10 Page - Analog Devices

Part No. AD1884
Description  High Definition Audio SoundMAX Codec
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD1884 Datasheet(HTML) 10 Page - Analog Devices

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AD1884
Table 3. AD1884 Pin Descriptions
Mnemonic
Pin No.
I/O
Description
DIGITAL INTERFACE
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
5
6
8
10
11
I
I
I/O
I
I
Link Serial Data Output. AD1884 input stream. Clocked on both edges of the
BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock .
Link Serial Data Input. AD1884 output stream clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. AD1884 master hardware reset.
DIGITAL I/O
GPIO_2
GPIO_1/MIC_BIAS-E
GPIO_0/EAPD
S/PDIF_OUT
30
31
47
48
I/O
I/O
I/O
O
General Purpose I/O/Microphone Bias for Port E. Capable of Hi-Z, 1.65 V, and 2.86 V.
Pin 31 shares functionality between GPIO_1 and MIC_BIAS_E. These functions are
mutually exclusive.
EAPD/General Purpose Input/Output pin. Pin 47 shares functionality between
GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function
takes priority over the GPIO function. By default, the pin is in a Hi-Z state. External
resistors should be used to insure the proper circuit state when this pin is in Hi-Z.
S/PDIF_OUT – Supports S/PDIF output.
JACK SENSE AND EAPD
SENSE_A/SRC_B
SENSE_B/SRC_A
13
34
I/O
I/O
Jack Sense A-D Input/Sense B drive.
Jack Sense E-F Input/Sense A drive.
ANALOG I/O
PCBEEP
Port E_L
Port E_R
Port F_L
Port F_R
CD_GND
Port B_L
Port B_R
Port C_L
Port C_R
MONO_OUT
Port D_L
Port D_R
Port A_L
Port A_R
12
14
15
16
17
19
21
22
23
24
32
35
36
39
41
LI
LI, MIC, LO
LI, MIC, LO
LI, LO
LI, LO
I
LI, MIC
LI, MIC
LI, MIC
LI, MIC
LO
HP, LO
HP, LO
HP, LO
HP, LO
Monaural Input from system for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD-Audio-Analog-Ground-Reference. Must be connected to AGND via a 0.1
μF
capacitor if not in use as CD_GND. MUST always be ac-coupled.
Front Panel stereo MIC/Line-In.
Front Panel stereo MIC/Line-In.
Rear Panel stereo MIC/Line-In.
Rear Panel stereo MIC/Line-In.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
FILTER/REFERENCE
VREF _FILT
MIC_BIAS-B
MIC_BIAS-C
DVCORE
27
28
29
1
O
O
O
O
Voltage Reference Filter.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Both MIC bias pins are capable of Hi-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on
Pin 33), Hi-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33).
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator. This pin must be connected to
filter caps: 10
μf, 1.0 μf, and 0.1 μf connected in parallel between Pin 1 and
DVSS (Pin 7).
POWER AND GROUND
DVIO 3.3V
DVSS
DVDD 3.3 V
3
7
9
I
I
I
Link Digital I/O Voltage Reference. 3.3 V
Digital Supply Return (ground).
Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the
internal digital core internal to the AD1884.
The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.
Rev. 0
|
Page 10 of 16
|
January 2007


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