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DSPIC33FJ128GP306 Datasheet(PDF) 5 Page - Microchip Technology |
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DSPIC33FJ128GP306 Datasheet(HTML) 5 Page - Microchip Technology |
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5 / 10 page  © 2006 Microchip Technology Inc. DS80279B-page 5 dsPIC33F 5. Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for 7 + 1 cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from 7 to 0. The counter is loaded with 7 at the end of the DISI instruction. If the user code executes another DISI on the instruction cycle where the DISI counter has become zero, the new DISI count is loaded, but the DISI state machine does not properly re- engage and continue to disable interrupts. At this point, all interrupts are enabled. The next time the user code executes a DISI instruction, the feature will act normally and block interrupts. In summary, it is only when a DISI execution is coincident with the current DISI count = 0, that the issue occurs. Executing a DISI instruction before the DISI counter reaches zero will not produce this error. In this case, the DISI counter is loaded with the new value, and interrupts remain disabled until the counter becomes zero. Work around When executing multiple DISI instructions within the source code, make sure that subsequent DISI instructions have at least one instruction cycle between the time that the DISI counter decre- ments to zero and the next DISI instruction. Alter- natively, make sure that subsequent DISI instructions are called before the DISI counter decrements to zero. 6. Module: Motor Control PWM Devices in the motor control family have a glitch in the PWMxL signal under certain conditions. The glitch is a brief high pulse during the low portion of the duty cycle. This error occurs when the module is configured in Single-Shot mode (PTMOD<1:0> = 01) with complementary output. It also occurs when resuming from a Fault condition in Free-Running mode (PTMOD<1:0) = 00) with complementary output. Work around None. 7. Module: Output Compare Module A glitch will be produced on an output compare pin under the following conditions: • The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register. • The output compare module is configured and enabled to drive the pin low at some later time (OCxCON = 0x0002 or OCxCON = 0x0003). When these events occur, the output compare module will drive the pin low for one instruction cycle (TCY) after the module is enabled. Work around None. However, the user may use a timer interrupt and write to the associated PORT register to control the pin manually. 8. Module: Output Compare Module in PWM Mode The output compare module will miss a compare event when the current duty cycle register (OCxRS) value is 0x0000 (0% duty cycle) and the OCxRS register is updated with a value of 0x0001. The compare event is missed only the first time a value of 0x0001 is written to OCxRS, and the PWM output remains low for one PWM period. Subsequent PWM high and low times occur as expected. Work around None. If the current OCxRS register value is 0x0000, avoid writing a value of 0x0001 to OCxRS. Instead, write a value of 0x0002; how- ever, in this case the duty cycle will be slightly different from the desired value. |
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