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DSPIC33FJ32MC202 Datasheet(PDF) 98 Page - Microchip Technology |
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DSPIC33FJ32MC202 Datasheet(HTML) 98 Page - Microchip Technology |
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98 / 292 page  dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DS70283B-page 96 Preliminary © 2007 Microchip Technology Inc. 7.1 CPU Clocking System The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provide seven system clock options: • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT, HS or EC) Oscillator • Primary Oscillator with PLL • Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator • FRC Oscillator with postscaler 7.1.1 SYSTEM CLOCK SOURCES The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: • XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is con- nected to the OSC1 and OSC2 pins. • HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. • EC (External Clock): External clock signal in the range of 0.8 MHz to 64 MHz. The external clock signal is directly applied to the OSC1 pin. The secondary (LP) oscillator is designed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 7.1.3 “PLL Configuration”. 7.1.2 SYSTEM CLOCK SELECTION The oscillator source used at a device Power-on Reset event is selected using Configuration bit set- tings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 20.1 “Configuration Bits” for further details.) The Initial Oscillator Selec- tion Configuration bits, FNOSC<2:0> (FOSC- SEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. The Configuration bits allow users to choose among 12 different clock modes, shown in Table 7-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to generate the device instruction clock (FCY). FCY defines the operating speed of the device, and speeds up to 40 MHz are supported by the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture. Instruction execution speed or device operating frequency, FCY, is given by: EQUATION 7-1: DEVICE OPERATING FREQUENCY 7.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 7-2. The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL’s Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor ‘N1’ is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’ by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor ‘N2.’ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by: EQUATION 7-2: FOSC CALCULATION FCY = FOSC/2 ( ) M N1*N2 FOSC = FIN* |
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