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DS28E01P-100+T Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS28E01P-100+T Datasheet(HTML) 3 Page - Dallas Semiconductor |
3 / 16 page Abridged Data Sheet DS28E01-100 3 of 16 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG (Notes 5, 19) 0.8 mA Programming Time tPROG (Note 20) 10 ms At 25°C 200k Write/Erase Cycles (En- durance) (Notes 21, 22) NCY At 85°C (worst case) 50k --- Data Retention (Notes 23, 24, 25) tDR At 85°C (worst case) 40 years SHA-1 ENGINE SHA Computation Current (Notes 5, 19) ILCSHA See full version of data sheet. mA SHA Computation Time (Note 5) tCSHA See full version of data sheet. ms Note 1: Specifications at TA = -40°C are guaranteed by design only and not production-tested. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If RPUP = 2.2kΩ, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 5: Guaranteed by design, characterization and/or simulation only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO needs to be less than or equal to VIL(MAX) at all times the master is driving IO to a logic-0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Note 14: Defines maximum possible bit rate. Equal to tW0L(min) + tREC(min). Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on IO if there is a DS28E01-100 present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min). Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 17: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF - ε and tW0Lmax + tF - ε respectively. Note 18: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF. Note 19: Current drawn from IO during EEPROM programming or SHA-1 computation interval. Note 20: See full version of data sheet. Note 21: Write-cycle endurance is degraded as TA increases. Note 22: Not 100% production-tested; guaranteed by reliability monitor sampling. Note 23: Data retention is degraded as TA increases. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes may become non-functional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write-capability after 10 years at 125°C or 40 years at 85°C. |
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