DS28EC20: 20Kb 1-Wire EEPROM

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OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the

DS28EC20. The DS28EC20 has four main data components: 1) 64-bit registration number, 2) 32-byte scratchpad,

3) eighty 32-byte pages of EEPROM, and 4) special function registers. The hierarchical structure of the 1-Wire

protocol is shown in Figure 2. The bus master must first provide one of the seven ROM (network) function

commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive Skip ROM, or

7) Overdrive Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the

device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol

required for these ROM function commands is described in Figure 9. After a ROM function command is

successfully executed, the memory functions become accessible and the master may provide any one of the five

memory function commands. The protocol for these commands is described in Figure 7. All data is read and written

least significant bit first.

Figure 2. Hierarchical Structure for 1-Wire Protocol

DS28EC20 Command Level:

1-Wire ROM Function

Commands (see Figure 9)

DS28EC20-Specific

Memory Function

Commands (see Figure 7)

Available

Commands:

Data Field

Affected:

Read ROM

Match ROM

Search ROM

Skip ROM

Resume

Overdrive Skip

Overdrive Match

64-bit Reg. #, RC-Flag

64-bit Reg. #, RC-Flag

64-bit Reg. #, RC-Flag

RC-Flag

RC-Flag

RC-Flag, OD-Flag

64-bit Reg. #, RC-Flag, OD-Flag

Write Scratchpad

Read Scratchpad

Copy Scratchpad

Read Memory

Extended Read Mem.

32-byte Scratchpad, Flags

32-byte Scratchpad

Data Memory, Register Page

Data Memory, Register Page

Data Memory, Register Page

64-BIT LASERED ROM

Each DS28EC20 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The

next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits.

See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register

and XOR gates as shown in Figure 4. The polynomial is X

CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas

Semiconductor iButton

The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a

time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the last

bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the

CRC returns the shift register to all 0s.

Figure 3. 64-Bit Lasered ROM

MSB

LSB

8-Bit

CRC Code

48-Bit Serial Number

8-Bit Family

Code (43h)

MSB

LSB

MSB

LSB

MSB

LSB

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