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DS1372 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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DS1372 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 12 page Status Register (08h) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 anytime the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC is insufficient to sup- port oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (i.e., noise, leak- age, etc.) exist. This bit remains at logic 1 until written to logic 0. Bits 6 to 1: These bits always read back as logic 0. Bit 0: Alarm Flag (AF). A logic 1 in the AF bit indicates that the alarm counter reached zero. If the AIE and INTCN bits are both set to logic 1, the SQW/INT pin goes low and remains low until AF is written to logic 0. This bit can only be written to logic 0. Attempting to write logic 1 leaves the value unchanged. ID Register A unique 64-bit lasered serial number is located in the address range 09h–10h. This serial number is divided into three parts. The first byte in register 09h contains a model number to identify the DS1372 device type. Registers 0Ah–0Fh contain a unique binary number. Register 10h contains a CRC byte used to validate the data in registers 09h–0Fh. All eight bytes of the serial number are read-only registers. The CRC byte is gener- ated with the polynomial equal to x8 + x5 + x4 + 1 (see Figure 3). The DS1372 is manufactured such that no two devices contain an identical number in locations 0Ah–0Fh. I2C Serial Data Bus The DS1372 supports a bidirectional I2C serial bus and data transmission protocol (Figure 4). A device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls the message is called a mas- ter. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP 8 _______________________________________________________________________________________ Bit # 7 6 5 4 3 2 1 0 Name OSF 0 0 0 0 0 0 AF Reset 1 0 0 0 0 0 0 0 Status Register (08h) 1ST STAGE 2ND STAGE 3RD STAGE 4TH STAGE 7TH STAGE 8TH STAGE 6TH STAGE 5TH STAGE X0 X1 X2 X3 X4 POLYNOMIAL = X8 + X5 + X4 + 1 INPUT DATA X5 X6 X7 X8 Figure 3. CRC Byte Polynomial I2C, 32-Bit, Binary Counter Clock with 64-Bit ID |
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