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DS1123L Datasheet(PDF) 8 Page - Dallas Semiconductor

Part # DS1123L
Description  3.3V, 8-Bit, Programmable Timing Element
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1123L Datasheet(HTML) 8 Page - Dallas Semiconductor

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3.3V, 8-Bit, Programmable Timing Element
8
______________________________________________________________________
Detailed Description
The DS1123L is an 8-bit programmable delay line that
can be adjusted between 256 different delay intervals.
Because of the design (see Figure 1) of the DS1123L, it
is possible to delay a signal by a whole period or more,
which allows the phase of the signal to be adjusted up
to a full 360°. Programming may be done using either an
8-bit parallel interface or a 3-wire serial interface. Using
the 3-wire interface, it is possible to cascade multiple
devices together for systems requiring multiple pro-
grammable delays without using additional I/O
resources. The DS1123L also features a reference delay
that is approximately equal to the step-zero delay, which
can be used to realize small relative delays.
Additionally, the DS1123L can function as a monostable
vibrator or an adjustable frequency oscillator.
Device Operation
This section details how to program the DS1123L using
both the parallel and serial interfaces, using the refer-
ence delay, and how to configure the chip to function as
a monostable vibrator or adjustable frequency oscillator.
Using the Parallel Programming Interface
To enable the DS1123L’s parallel interface, P/S must be
connected to ground. This allows the data on the paral-
lel inputs (P0 to P7) to pass through the latch, which
are transparent when latch enable (LE) is at a high
input level. When LE is at a low level, the data is
latched until LE is returned to a high state. If the parallel
inputs are going to be used to hardwire a delay, LE
must be connected to VCC to allow the setting to take
DS1123L
REFERENCE
DELAY
PROGRAMMABLE
DELAY
IN
P/S
LE
P3-P7
P0/Q
P1/CLK
P2/D
5
8
8
8-BIT LATCH
8-BIT INPUT
REGISTER
OUTPUT
MODE
CONTROL
OUT/OUT
REF/PWM
PIN
NAME
FUNCTION
1IN
Input Signal to be Delayed, PWM
Trigger
2
LE
Input-Latch Enable
3
P0/Q
Input P0 (Parallel Mode)/
Serial Data Output (Serial Mode)
4
P1/CLK
Input P1 (Parallel Mode)/
Serial Clock (Serial Mode)
5
P2/D
Input P2 (Parallel Mode)/
Serial Data Input (Serial Mode)
6
P3
Input P3
7
P4
Input P4
8
GND
Ground
9
REF/PWM
Reference Output/PWM Output
10
P5
Input P5
11
MS
Input Mode Select
MS = 0 for Delay Function,
MS = 1 for Oscillator or PWM
12
P6
Input P6
13
P7
Input P7
14
P/S
Parallel/Serial Programming Select
15
OUT/OUT
Delay Output or Inverted Output
16
VCC
Power Supply (3.3V)
Pin Description
Functional Diagram
tD
tD
tD
tD
OUT
IN
256 LINE
DECODER
8-BIT LATCH VALUE
256 CONTROL
LINES
REF
255 UNIT
DELAY CELLS
Figure 1. DS1123L Conceptual Design


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