TDA8752BH datasheet(18/36 Pages) PHILIPS

Part #	TDA8752BH

Description	Triple high-speed Analog-to-Digital Converter 110 Msps ADC

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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18 / 36 page

2000 Jan 10

18

Philips Semiconductors

Preliminary speciﬁcation

Triple high-speed Analog-to-Digital

Converter 110 Msps (ADC)

TDA8752B

OFFSET REGISTER

This register controls the clamp level for the

RGB channels. The relationship between the

programming code and the level of the clamp code is given

in Table 2.

Table 2

Coding

The default programmed value is:

• Programmed code = 127

• Clamp code = 0

• ADC output = 0.

COARSE AND FINE REGISTERS

These two registers enable the gain control, the AGC gain

with the coarse register and the reference voltage with the

fine register. The coarse register programming equation is

as follows:

Where: Vref = 2.5 V.

The gain correspondence is given in Table 3. The gain is

linear with reference to the programming code (NFINE = 0).

Table 3

Gain correspondence (COARSE)

The default programmed value is as follows:

• N

COARSE =32

• Gain = 0.825

• Vi to be full-scale = 1.212.

To modulate this gain, the fine register is programmed

using the above equation. With a full-scale ADC input, the

fine register resolution is a 1

⁄2LSB peak-to-peak

(see Table 4 for NCOARSE = 32).

Table 4

Gain correspondence (FINE)

The default programmed value is: NFINE =0.

CONTROL REGISTER

COAST and HSYNC signals can be inverted by setting the

I2C-bus control bits V level and H level respectively. When

V level and H level are set to zero respectively, COAST

and HSYNC are active HIGH.

The bit ‘edge’ defines the rising or falling edge of CKREF

to synchronise the PLL. It will be on the rising edge if the

bit is at logic 0 and on the falling edge if the bit is at logic 1.

The bits Up and Do are used for the test, to force the

charge pump current. These bits have to be logic 0 during

normal use.

The bits Ip0, Ip1 and Ip2 control the charge pump current,

to increase the bandwidth of the PLL, as shown in Table 5.

PROGRAMMED

CODE

CLAMP CODE

ADC OUTPUT

0

−63.5

underﬂow

1

−63

2

−62.5

↓↓

127

0

↓↓↓

254

63.5

63 or 64

255

64

256

120

↓↓↓

287

136

GAIN

N

COARSE

1

+

V

ref 1

N

FINE

32

16

×

-------------------

–





---------------------------------------------

1

16

------

×

N

COARSE

1

+

V

ref 512

N

FINE

–

()

-----------------------------------------------

32

×

=

NCOARSE

GAIN

Vi TO BE

FULL-SCALE

32

0.825

1.212

99

2.5

0.4

NFINE

GAIN

Vi TO BE

FULL-SCALE

0

0.825

1.212

31

0.878

1.139

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