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IS61LV25616L Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc

Part No. IS61LV25616L
Description  256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
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IS61LV25616L Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc

 
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
IS61LV25616L
ISSI®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
DATA UNDEFINED
t WC
ADDRESS 1
ADDRESS 2
t WC
HIGH-Z
t PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t HD
t SA
t HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATAIN
VALID
t LZWE
t SD
t PBW
DATAIN
VALID
t SD
t HD
t SA
t HA
t HA
Notes:
1. The internal Write time is defined by the overlap of
CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The
t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with
OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3.
WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.


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