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U632H16 Datasheet(PDF) 1 Page - Simtek Corporation |
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U632H16 Datasheet(HTML) 1 Page - Simtek Corporation |
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1 / 15 page  U632H16 1 August 15, 2006 STK Control #ML0046 Rev 1.1 PowerStore 2K x 8 nvSRAM Pin Configuration Pin Description Top View Signal Name Signal Description A0 - A10 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable VCCX Power Supply Voltage VSS Ground VCAP Capacitor HSB Hardware Controlled Store/Busy Package: SOP28 (300 mil) Description The U632H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab- led. The U632H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi- des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 μF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U632H16 combines the high per- formance and ease of use of a fast SRAM with nonvolatile data inte- grity. STORE cycles also may be initia- ted under user control via a soft- ware sequence or via a single pin (HSB). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initia- ted by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. 1 VCAP VCCX 28 2 n.c. W 27 4 A6 A8 25 5 A5 A9 24 3 A7 HSB 26 6 A4 n.c. 23 7 A3 G 22 8 A2 A10 21 12 DQ1 DQ5 17 9 A1 E 20 10 A0 DQ7 19 11 DQ0 DQ6 18 13 DQ2 DQ4 16 14 VSS DQ3 15 SOP Features High-performance CMOS non- volatile static RAM 2048 x 8 bits 25 ns Access Times 12 ns Output Enable Access Times ICC = 15 mA at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using external capacitor Hardware or Software initiated STORE (STORE Cycle Time < 10 ms) Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 20 μs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7-HBM) RoHS compliance and Pb- free Not Recommended For New Designs |
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