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STK16C88 Datasheet(PDF) 8 Page - Simtek Corporation

Part # STK16C88
Description  32Kx8 AutoStore nvSRAM
Download  12 Pages
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Manufacturer  SIMTEK [Simtek Corporation]
Direct Link  http://www.simtek.com
Logo SIMTEK - Simtek Corporation

STK16C88 Datasheet(HTML) 8 Page - Simtek Corporation

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February, 2007
Document Control #ML0018 Rev 0.3
The AutoStore+ STK16C88 is a fast 32K x 8 SRAM
that does not lose its data on power-down. The data
is preserved in integral QuantumTrap non-volatile
storage elements when power is lost. Automatic
STORE on power-down and automatic RECALL on
power-up guarantee data integrity without the use of
Note that the STK16C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1
μF connected between V
and V
SS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
The STK16C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
0-14 determines which of the 32,768 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of t
AVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at t
at t
GLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the t
AVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7 will be writ-
ten into the memory if it is valid t
DVWH before the end
of a W controlled WRITE or t
DVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
The STK16C88’s automatic STORE on power-down
is completely transparent to the system. The
STORE initiation takes less than 500ns when power
is lost (V
CC < VSWITCH) at which point the part depends
only on its internal capacitor for STORE completion.
If the power supply drops faster than 20
before Vcc reaches Vswitch, then a 2.2 ohm resistor
should be inserted between Vcc and th system sup-
ply to avoid a momentary excess of current between
Vcc and internal capacitor.
In order to prevent unneeded STORE operations,
automatic STOREs will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether or not a WRITE operation has taken place.
During power up, or after any low-power condition
CC < VRESET), an internal RECALL request will be
latched. When V
CC once again exceeds the sense
voltage of V
SWITCH, a RECALL cycle will automatically
be initiated and will take t
RESTORE to complete.
If the STK16C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be cor-
rupted. To help avoid this situation, a 10k
Ω resistor
should be connected either between W and system
CC or between E and system VCC.
The STK16C88 software STORE cycle is initiated
by executing sequential READ cycles from six spe-
cific address locations. During the STORE cycle,
previous non-volatile data is erased and then the
SRAM contents are written to the non-volatile stor-
age elements. Once a STORE cycle is initiated, fur-
ther inputs and outputs are disabled until the cycle is
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
sequence must be performed:

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