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STK11C88-3PF45I Datasheet(PDF) 8 Page - Simtek Corporation |
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STK11C88-3PF45I Datasheet(HTML) 8 Page - Simtek Corporation |
8 / 10 page STK11C88-3 March 2006 8 Document Control # ML0013 rev 0.2 Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvola- tile information is transferred into the SRAM cells. After the t RECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. POWER-UP RECALL During power up, or after any low-power condition (V CC < VRESET ), an internal RECALL request will be latched. When V CC once again exceeds the sense voltage of V SWITCH, a RECALL cycle will automatically be initiated and will take t RESTORE to complete. If the STK11C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system V CC or between E and system VCC. HARDWARE PROTECT The STK11C88-3 offers hardware protection against inadvertent STORE operation during low- voltage conditions. When V CC < VSWITCH, all software STORE operations are inhibited. LOW AVERAGE ACTIVE POWER The STK11C88-3 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between I CC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial tem- perature range, V CC = 3.6V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles.If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading. Figure 2: ICC (max) Reads 0 10 20 30 40 50 50 100 150 200 Cycle Time (ns) TTL CMOS Figure 3: ICC (max) Writes 0 10 20 30 40 50 50 100 150 200 Cycle Time (ns) TTL CMOS |
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