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PIC18F4431 Datasheet(PDF) 90 Page - Microchip Technology |
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PIC18F4431 Datasheet(HTML) 90 Page - Microchip Technology |
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90 / 400 page  PIC18F2331/2431/4331/4431 DS39616C-page 88 Preliminary © 2007 Microchip Technology Inc. REGISTER 7-1: EECON1: FLASH PROGRAM/DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally bit 2 WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Note 1: When a WRERR occurs, the EEPGD and FREE bits are not cleared. This allows tracing of the error condition. |
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