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PIC16F87 Datasheet(PDF) 85 Page - Microchip Technology

Part # PIC16F87
Description  18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F87 Datasheet(HTML) 85 Page - Microchip Technology

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 2005 Microchip Technology Inc.
DS30487C-page 83
PIC16F87/88
9.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• Driven high
•Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit, CCP1IF, is set.
FIGURE 9-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
9.2.1
CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the TRISB<x> bit.
9.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
9.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1.
TABLE 9-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
CCP1 pin
TRISB<x>
CCP1CON<3:0>
Mode Select
Output Enable
Special Event Trigger will:
Reset Timer1 but not set interrupt flag bit, TMR1IF
(PIR1<0>)
Set bit GO/DONE (ADCON0<2>) which starts an A/D
conversion
Note 1: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data
latch.
2: The TRISB bit (0 or 3) is dependent upon
the
setting
of
configuration
bit
12
(CCPMX).
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh,8Bh
10BH,18Bh
INTCON
GIE
PEIE
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
0Ch
PIR1
ADIF(1)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF -000 0000 -000 0000
8Ch
PIE1
ADIE(1)
RCIE
TXIE
SSPIE
CCP1IE TMR2IE
TMR1IE -000 0000 -000 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note
1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.


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