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MCP3909 Datasheet(PDF) 5 Page - Microchip Technology |
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MCP3909 Datasheet(HTML) 5 Page - Microchip Technology |
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© 2006 Microchip Technology Inc. DS22025A-page 5 MCP3909 TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V, AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C. Parameter Sym Min Typ Max Units Comment Frequency Outputs FOUT0 and FOUT1 Pulse Width (Logic Low) tFW — 275 — ms 984376 MCLK periods (Note 1) HFOUT Pulse Width tHW — 90 — ms 322160 MCLK periods (Note 2) FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s HFOUT Pulse Period tHP Refer to Equation 4-2 s FOUT0 to FOUT1 Falling-Edge Time tFS2 — 0.5 tFP — FOUT0 to FOUT1 Minimum Sepa- ration tFS — 4/MCLK — Digital I/O FOUT0 and FOUT1 Output High Voltage VOH 4.5 —— VIOH = 12 mA, DVDD = 5.0V FOUT0 and FOUT1 Output Low Voltage VOL —— 0.5 V IOL = 12 mA, DVDD = 5.0V HFOUT and NEG Output High Voltage VOH 4.5 —— VIOH = 12 mA, DVDD = 5.0V HFOUT and NEG Output Low Voltage VOL —— 0.5 V IOL = 12 mA, DVDD = 5.0V High-Level Input Voltage (All Digital Input Pins) VIH 2.4 —— VDVDD = 5.0V Low Level Input Voltage (All Digital Input Pins) VIL —— 0.85 V DVDD = 5.0V Input Leakage Current —0.1 ±1 µA VIN = 0, VIN = DVDD Pin Capacitance —— 10 pF (Note 3) Serial Interface Timings (Note 4) Output Data Rate fADC —MCLK/256 — Serial Clock Frequency fCLK —20 MHz VDD = 5V Window for serial mode entry codes tWINDOW — — 8/MCLK — Last bit must be clocked in before this time. Window start time for serial mode entry codes tWINSET 1/MCLK — — — First bit must be clocked in after this time. Serial Clock High Time tHI 10 — 40 ns Serial Clock Low Time tLO 30 — 20 ns CS Fall to First Rising CLK Edge tSUCS 15 — — ns Data Input Setup Time tSU 10 — — ns Data Input Hold Time tHD — — 10 ns CS Rise to Output Disable tDIS —— 150 ns CLK Fall to Output Data Valid tDO — — 30 ns Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP. 2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0 equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz 3: Specified by characterization, not production tested. 4: Serial timings specified and production tested with 180 pF load. |
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