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TSC2004IRTJT Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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TSC2004IRTJT Datasheet(HTML) 7 Page - Burr-Brown (TI) |
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7 / 54 page  www.ti.com TIMING REQUIREMENTS: I 2C Fast Mode (f SCL = 400kHz) (1) TSC2004 SBAS408A – JUNE 2007 – REVISED AUGUST 2007 All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 μs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 μs SCL clock frequency fSCL 400 kHz Bus free time between a STOP and START tBUF 1.3 μs condition Hold time (repeated) START condition tHD, STA 0.6 μs Low period of SCL clock tLOW 1.3 μs High period of the SCL clock tHIGH 0.6 μs Setup time for a repeated START condition tSU, STA 0.6 μs Data hold time tHD, DAT 0 0.9 μs Data setup time tSU, DAT 100 ns Rise time for both SDA and SCL clock signals tR Cb = total bus capacitance 20 + 0.1 × C b 300 ns (receiving) Fall time for both SDA and SCL clock signals tF Cb = total bus capacitance 20 + 0.1 × C b 300 ns (receiving) Fall time for both SDA and SCL clock signals tOF Cb = total bus capacitance 20 + 0.1 × C b 250 ns (transmitting) Setup time for STOP condition tSU, STO 0.6 μs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 50 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 36. TIMING REQUIREMENTS: I 2C High-Speed Mode (f SCL = 1.7MHz) (1) All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 μs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 μs SCL clock frequency fSCL 1.7 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 320 ns High period of the SCL clock tHIGH 120 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 150 ns Data setup time tSU, DAT 10 ns Rise time for SCL clock signal (receiving) tR Cb = total bus capacitance 20 80 ns Rise time for SDA clock signal (receiving) tR Cb = total bus capacitance 20 160 ns Fall time for SCL clock signal (receiving) tF Cb = total bus capacitance 20 80 ns Fall time for SDA clock signal (receiving) tF Cb = total bus capacitance 20 160 ns Fall time for both SDA and SCL clock signals tOF Cb = total bus capacitance 10 80 ns (transmitting) Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 10 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 36. 7 Submit Documentation Feedback |
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