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P89V660FBC Datasheet(PDF) 6 Page - NXP Semiconductors |
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P89V660FBC Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 89 page P89V660_662_664_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 2 May 2007 6 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 5.2 Pin description Table 3. Pin description Symbol Pin Type Description TQFP44 PLCC44 P0[0] to P0[7] I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have ‘1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when making the transition to ‘1’s. External pull-ups are required as a general purpose I/O port. P0[0]/AD0 37 43 I/O P0[0] — Port 0 bit 0. I/O AD0 — Address/data bit 0. P0[1]/AD1 36 42 I/O P0[1] — Port 0 bit 1. I/O AD1 — Address/data bit 1. P0[2]/AD2 35 41 I/O P0[2] — Port 0 bit 2. I/O AD2 — Address/data bit 2. P0[3]/AD3 34 40 I/O P0[3] — Port 0 bit 3. I/O AD3 — Address/data bit 3. P0[4]/AD4 33 39 I/O P0[4] — Port 0 bit 4. I/O AD4 — Address/data bit 4. P0[5]/AD5 32 38 I/O P0[5] — Port 0 bit 5. I/O AD5 — Address/data bit 5. P0[6]/AD6 31 37 I/O P0[6] — Port 0 bit 6. I/O AD6 — Address/data bit 6. P0[7]/AD7 30 36 I/O P0[7] — Port 0 bit 7. I/O AD7 — Address/data bit 7. P1[0] to P1[7] I/O with internal pull-up Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 pins are pulled high by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P1[5], P1[6], P1[7] have high current drive of 16 mA. P1[0]/T2 40 2 I/O P1[0] — Port 1 bit 0. I T2 — External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 P1[1]/T2EX 41 3 I/O P1[1] — Port 1 bit 1. I T2EX: Timer/Counter 2 capture/reload trigger and direction control P1[2]/ECI 42 4 I/O P1[2] — Port 1 bit 2. I ECI — External clock input. This signal is the external clock input for the PCA. P1[3]/CEX0 43 5 I/O P1[3] — Port 1 bit 3. I/O CEX0 — Capture/compare external I/O for PCA Module 0. Each capture/compare module connects to a Port 1 pin for external I/O. When not used by the PCA, this pin can handle standard I/O. |
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