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LS7166 Datasheet(PDF) 6 Page - LSI Computer Systems |
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LS7166 Datasheet(HTML) 6 Page - LSI Computer Systems |
6 / 15 page TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7, VDD = 3V to 5.5V, TA = 0˚ to 85˚C, unless otherwise specified) Parameter Symbol Min.Value Max.Value Unit Clock A/B "Low” TCL 18 No Limit ns Clock A/B "High" TCH 22 No Limit ns Clock A/B Frequency fc 0 25 MHz (See NOTE 1) Clock UP/DN Reversal TUDD 100 - ns Delay LCTR Positive edge to TLC 100 - ns the next A/B positive or negative edge delay Clock A/B to TCBL - 65 ns CY/BW/COMP "low" propagation delay Clock A/B to TCBH - 85 ns CY/BW/COMP "high" propagation delay LCTR and LLTC pulse TLCW 60 - ns width Clock A/B to CYT, BWT TTFH - 100 ns and COMPT "high" propagation delay Clock A/B to CYT, BWT TTFL - 100 ns and COMPT "low" progagation delay WR pulse width TWR 60 - ns RD to data out delay TR - 110 ns (CL=20pF) CS, RD Terminate to TRT - 30 ns Data-Bus Tri-State Data-Bus set-up TDS 30 - ns time for WR Data-Bus hold time for WR TDH 30 - ns CS set-up time for RD TSRS 0 - ns CS hold time for RD TSRH 0 - ns Back to Back RD delay TRR 60 - ns RD to WR delay - 60 - ns C/D set-up time for RD TCRS 0 C/D hold time for RD TCRH 30 C/D set-up time for WR TCWS 30 - ns C/D hold time for WR TCWH 30 - ns CS set-up time for WR TSWS 60 - ns CS hold time for WR TSWH 0 - ns Back to Back WR delay Tww 60 - ns WR to RD delay - 60 - ns Quadrature Mode: Clock A/B Validation delay TCQV - 160 ns (See NOTE 1) A and B phase delay TPH 208 - ns Clock A/B frequency fCQ - 1.2 MHz CY, BW, COMP pulse width TCBW 85 200 ns NOTE 1: In quadrature mode A/B inputs are filtered and required to be stable for at least TCQV length to be valid. 7166-011705-6 |
Similar Part No. - LS7166_06 |
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Similar Description - LS7166_06 |
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