ISP1506B datasheet(10/79 Pages) NXP

Part #	ISP1506B

Description	ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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10 / 79 page

ISP1506A_ISP1506B_1

Product data sheet

Rev. 01 — 30 May 2007

10 of 79

NXP Semiconductors

ISP1506A; ISP1506B

ULPI HS USB OTG transceiver

which also shows a typical OTG VBUS load. The value of Ccp(C_A)-(C_B) depends on the

amount of current drive required. If the internal charge pump is not used, the Ccp(C_A)-(C_B)

capacitor is not required.

For details on the C_A and C_B pins, see Section 7.9.7.

7.7 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias analog circuitry.

This band gap requires an accurate external reference resistor, RRREF, connected

between the RREF and GND pins. For details, see Section 16.

7.8 Power-On Reset (POR)

The ISP1506 has an internal power-on-reset circuit that resets all internal logic on

power-up. The ULPI interface is also reset on power-up.

Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset

command over the ULPI bus to ensure correct operation of the ISP1506.

7.9 Detailed description of pins

7.9.1 DATA[3:0]

Dual-edge bidirectional data bus. The USB link must drive DATA[3:0] to LOW when the

ULPI bus is idle. When the link has data to transmit to the PHY, it drives a nonzero value.

The data bus can be reconﬁgured to carry various data types, as given in Section 8 and

Section 9.

7.9.2 VCC(I/O)

The input power pin that sets the I/O voltage level. For details, see Section 12, Section 13

and Section 16. VCC(I/O) provides power to on-chip pads of the following pins:

• CLOCK

• DATA[3:0]

• DIR

• NXT

• RESET_N/PSW_N

• STP

Fig 3.

External capacitors connection

004aaa600

ISP1506

VBUS

C_B

C_A

Ccp(C_A)-(C_B)

OTG VBUS

4.7

µF

0.1

µF

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