Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

AZ100EP16FE Datasheet(PDF) 1 Page - Arizona Microtek, Inc

Part No. AZ100EP16FE
Description  ECL/PECL High Speed VCSEL Driver with Variable Output Swing or Limiting Amplifier
Download  5 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AZM [Arizona Microtek, Inc]
Homepage  http://azmicrotek.com
Logo 

AZ100EP16FE Datasheet(HTML) 1 Page - Arizona Microtek, Inc

   
Zoom Inzoom in Zoom Outzoom out
 1 / 5 page
background image
AZ100EP16FE
ECL/PECL High Speed VCSEL Driver with
Variable Output Swing or Limiting Amplifier
1630 S. STAPLEY DR., SUITE 127
• MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Silicon-Germanium for High Speed
Operation
<100ps Typical Rise/Fall Times
Optimized for 0.622 to 2.5Gbps
Fiber Applications
S-Parameter (.s2p) and IBIS Model
Files available on Arizona Microtek
Website
DESCRIPTION
The AZ100EP16FE is a Silicon–Germanium (SiGe) differential VCSEL driver with variable output swing or
limiting post amplifier. The 100EP16FE is optimized for OC-12, OC-24, OC-48, Ethernet, Sonnet, Fiber Channel or
related applications at data rates up to 2.5Gbps. An input controls the amplitude of the Q/Q
¯ outputs, which allows
compensation for differing VCSEL characteristics.
The operational range of the 100EP16FE control input, VCTRL, is from VREF (full swing) to VCC (small swing).
For post amplifier applications, maximum swing is achieved by leaving the VCTRL pin open or by tying it to the
negative supply pin (VEE). Simple control of the output swing can be obtained by a variable resistor between the
VREF and VCC pins, with the wiper driving VCTRL. A typical application circuit is described in this Data Sheet.
The 100EP16FE also provides a VREF output which functions as a DC bias for input AC coupling to the device.
The VREF pin should be used only as a bias for the 100EP16FE as its current sink/source capability is limited. When
used, the VREF pin should be bypassed to ground via a 0.01μF capacitor.
The maximum DC output current should be kept below 16mA. Connecting each output (Q/Q
¯) to VEE with a
180
Ω resistor is typically used. The load is then AC coupled from the output. DC and AC symmetrical loading of
the Q/Q
¯ outputs will provide the best output wave shape.
Under open input conditions for D/D
¯, the Q/Q
¯ outputs are not guaranteed.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
FUNCTION
D, D
¯
Data Inputs
VCTRL
Output Swing Control
Q, Q
¯
Data Outputs
VREF
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
8
5
6
7
4
3
2
1
VCC
D
VEE
Q
Q
VREF
D
VCTRL
TSSOP 8
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER
MARKING
NOTES
TSSOP 8
AZ100EP16FET
AZHP
16FE
1,2
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2
Date code on underside of part. Format: “Y” or “YY” for year followed by “WW”
for week.


Html Pages

1  2  3  4  5 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn