Lattice Semiconductor

ispPAC-POWR6AT6 Data Sheet

4

1

TDO

Digital Output

JTAG Test Data Out

3

TCK

Digital Input

JTAG Test Clock Input

5

TMS

Digital Input

JTAG Test Mode Select; Internal Pullup

4

TDI

Digital Input

JTAG Test Data In; Internal Pullup

10

SCL

Digital Input

I

11

SDA

Digital I/O

I

1. Open-drain outputs require an external pull-up resistor to a supply.

2. Normally asserted low, but can be programmed to assert high (open) if desired.

3. The VMONxGS inputs are the ground sense line for each given VMON pin. The VMON input pins along with the VMONxGS ground sense

pins implement a differential pair for each voltage monitor to allow remote sense at the load. VMONxGS lines must be connected and are

not to exceed -0.3V to +0.3V in reference to the GND pin.

4. VCCA and VCCD pins must be connected together on the circuit board.

Pin Descriptions (Cont.)

Number

Name

Pin Type

Voltage Range

Description