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DS3100 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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DS3100 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 226 page DS3100 Stratum 3/3E Timing Card IC 6 of 226 LIST OF TABLES Table 1-1. Applicable Telecom Standards................................................................................................................... 7 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 15 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 16 Table 6-3. BITS Receiver Pin Descriptions ............................................................................................................... 17 Table 6-4. BITS Transmitter Pin Descriptions ........................................................................................................... 18 Table 6-5. Global Pin Descriptions ............................................................................................................................ 19 Table 6-6. Parallel Interface Pin Descriptions ........................................................................................................... 20 Table 6-7. SPI Bus Mode Pin Descriptions ............................................................................................................... 21 Table 6-8. JTAG Interface Pin Descriptions .............................................................................................................. 21 Table 6-9. General-Purpose I/O Pin Descriptions ..................................................................................................... 21 Table 6-10. Power-Supply Pin Descriptions .............................................................................................................. 22 Table 7-1. GR-1244 Stratum 3E/3 Stability Requirements........................................................................................ 25 Table 7-2. Input Clock Capabilities ............................................................................................................................ 27 Table 7-3. Locking Frequency Modes ....................................................................................................................... 28 Table 7-4. Default Input Clock Priorities .................................................................................................................... 31 Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 38 Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 42 Table 7-7. Output Clock Capabilities ......................................................................................................................... 44 Table 7-8. Digital1 and Digital2 Frequencies............................................................................................................. 47 Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) .............................................................................. 48 Table 7-10. T0 APLL Frequency to T0 Path Configuration ....................................................................................... 48 Table 7-11. T4 APLL Frequency to T4 Path Configuration ....................................................................................... 49 Table 7-12. OC1 to OC7 Output Frequency Selection .............................................................................................. 50 Table 7-13. Possible Frequencies for OC1 to OC7 ................................................................................................... 50 Table 7-14. Equipment Redundancy Methodology ................................................................................................... 54 Table 7-15. Transformer Specifications..................................................................................................................... 67 Table 7-16. DS1 Alarm Criteria.................................................................................................................................. 68 Table 7-17. E1 Alarm Criteria .................................................................................................................................... 70 Table 7-18. E1 Sync and Resync Criteria ................................................................................................................. 70 Table 7-19. 2048kHz Synchronization Interface Specification .................................................................................. 73 Table 7-20. 6312kHz Synchronization Interface Specification .................................................................................. 73 Table 7-21. Composite Clock Variations ................................................................................................................... 74 Table 7-22. GR-378 Composite Clock Interface Specification .................................................................................. 76 Table 7-23. G.703 Synchronization Interfaces Specification..................................................................................... 76 Table 7-24. Microprocessor Interface Modes ............................................................................................................ 77 Table 8-1. Top-Level Memory Map............................................................................................................................ 81 Table 8-2. Core Register Map ................................................................................................................................... 82 Table 8-3. BITS Transceiver Register Map ............................................................................................................. 147 Table 9-1. JTAG Instruction Codes ......................................................................................................................... 201 Table 9-2. JTAG ID Code ........................................................................................................................................ 202 Table 10-1. Recommended DC Operating Conditions............................................................................................ 203 Table 10-2. DC Characteristics................................................................................................................................ 203 Table 10-3. CMOS/TTL Pins ................................................................................................................................... 204 Table 10-4. LVDS Pins ............................................................................................................................................ 204 Table 10-5. LVPECL Pins........................................................................................................................................ 205 Table 10-6. AMI Composite Clock Pins................................................................................................................... 206 Table 10-7. Recommended External Components for Output Clock OC8.............................................................. 206 Table 10-8. Input Clock Timing................................................................................................................................ 207 Table 10-9. Input Clock to Output Clock Delay ....................................................................................................... 207 Table 10-10. Output Clock Phase Alignment, Frame Sync Alignment Mode......................................................... 207 Table 10-11. BITS Receiver Timing......................................................................................................................... 208 Table 10-12. BITS Transmitter Timing..................................................................................................................... 209 Table 10-13. Parallel Interface Timing..................................................................................................................... 210 Table 10-14. SPI Interface Timing ........................................................................................................................... 213 Table 10-15. JTAG Interface Timing........................................................................................................................ 214 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 215 Table 13-1. Thermal Properties, Natural Convection .............................................................................................. 222 |
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