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DS3100 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part No. DS3100
Description  Stratum 3/3E Timing Card IC
Download  226 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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DS3100 Datasheet(HTML) 3 Page - Maxim Integrated Products

 
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DS3100 Stratum 3/3E Timing Card IC
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7.7.12 Jitter and Wander Transfer........................................................................................................... 42
7.7.13 Output Jitter and Wander ............................................................................................................. 43
7.8 OUTPUT CLOCK CONFIGURATION.................................................................................................44
7.8.1
Signal Format Configuration......................................................................................................... 45
7.8.2
Frequency Configuration .............................................................................................................. 45
7.9 EQUIPMENT REDUNDANCY CONFIGURATION.................................................................................54
7.9.1
Master-Slave Pin Feature............................................................................................................. 55
7.9.2
Master-Slave Output Clock Phase Alignment .............................................................................. 55
7.9.3
Master-Slave Frame and Multi-Frame Alignment with the SYNC2K Pin ..................................... 56
7.10 MULTIPROTOCOL BITS TRANSCEIVERS ........................................................................................58
7.10.1 Master Clock Connections ........................................................................................................... 59
7.10.2 Receiver Clock Connections ........................................................................................................ 59
7.10.3 Transmitter Clock Connections .................................................................................................... 61
7.10.4 Line Interface Unit ........................................................................................................................ 62
7.10.5 DS1 Synchronization Interface..................................................................................................... 68
7.10.6 E1 Synchronization Interface ....................................................................................................... 70
7.10.7 G.703 2048kHz Synchronization Interface................................................................................... 72
7.10.8 G.703 Appendix II 6312kHz Japanese Synchronization Interface............................................... 73
7.11 COMPOSITE CLOCK RECEIVERS AND TRANSMITTER......................................................................74
7.11.1 IC1 and IC2 Receivers ................................................................................................................. 75
7.11.2 OC8 Transmitter ........................................................................................................................... 75
7.12 MICROPROCESSOR INTERFACES ..................................................................................................77
7.12.1 Parallel Interface Modes............................................................................................................... 77
7.12.2 SPI Interface Mode....................................................................................................................... 77
7.13 RESET LOGIC ..............................................................................................................................79
7.14 POWER-SUPPLY CONSIDERATIONS ..............................................................................................80
7.15 INITIALIZATION .............................................................................................................................80
8. REGISTER DESCRIPTIONS ...............................................................................................81
8.1 STATUS BITS ...............................................................................................................................81
8.2 CONFIGURATION FIELDS ..............................................................................................................81
8.3 MULTIREGISTER FIELDS...............................................................................................................81
8.4 CORE REGISTER DEFINITIONS......................................................................................................82
8.5 BITS TRANSCEIVER REGISTER DEFINITIONS ..............................................................................147
9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................198
9.1 JTAG DESCRIPTION ..................................................................................................................198
9.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ...........................................................199
9.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ....................................................................201
9.4 JTAG TEST REGISTERS ............................................................................................................202
10. ELECTRICAL CHARACTERISTICS..................................................................................203
10.1 DC CHARACTERISTICS ..............................................................................................................203
10.2 INPUT CLOCK TIMING .................................................................................................................207
10.3 OUTPUT CLOCK TIMING .............................................................................................................207
10.4 BITS TRANSCEIVER TIMING .......................................................................................................208
10.5 PARALLEL INTERFACE TIMING ....................................................................................................210
10.6 SPI INTERFACE TIMING..............................................................................................................213
10.7 JTAG INTERFACE TIMING ..........................................................................................................214
11. PIN ASSIGNMENTS ..........................................................................................................215
12. PACKAGE INFORMATION ...............................................................................................221
12.1 256-PIN CSBGA (17MM X 17MM) (56-G6017-001)....................................................................221
13. THERMAL INFORMATION ................................................................................................222


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