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ABVFM Datasheet(PDF) 1 Page - Abracon Corporation

Part No. ABVFM
Description  CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL
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Maker  ABRACON [Abracon Corporation]
Homepage  http://www.abracon.com/index.htm
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ABVFM Datasheet(HTML) 1 Page - Abracon Corporation

   
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Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Jitter (12KHz - 20MHz)
ABRACON IS
ABRACON IS
ISO 9001 / QS 9000
ISO 9001 / QS 9000
CERTIFIED
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
WITH VOLTAGE CONTROL
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
|||||||||||||||
ABVFM SERIES
STANDARD SPECIFICATIONS:
APPLICATIONS:
• xDSL, Cable Modems
• Customer Premise Equipment (CPE)
• ATM, SONET, SDH, STB
• LAN / WAN Data Communications Equip.
FEATURES:
• Based on a proprietary analog multiplier
• Tri-State Output
• Ultra low Phase Jitter
• 155.52MHz,
311.04MHz, 622.08MHz applications
• 2.5V to 3.3V +/- 10% operation
• Ceramic SMD, low profile package
PARAMETERS
PECL
60 MHz to 320 MHz
0°C to + 70°C (see options)
- 55°C to + 125°C
± 100 ppm max. (see options)
2.5V - 3.3 Vdc ± 10%
RMS phase jitter < 0.6pS
period jitter < 20pS peak to peak
Low Phase Noise
Aging (PPM/year)
Pullability
-130 dBc/Hz @ 1kHz Offset from 212.5MHz
-140 dBc/Hz @ 10kHz Offset from 212.5MHz
-145 dBc/Hz @ 100kHz Offset from 212.5MHz
TBD Per Crystal
+/- 50ppm
5.0 x 7.0 x 1.8mm
Supply Current (IDD)[Fout = 212.50MHz]
Output Clock Duty Cycle @ VDD-1.3V
Output High Voltage
Output Low Voltage
Clock Rise time (tr) @ 20/80%
Clock Fall time (tf) @ 80/20%
58mA min, 65mA typical, 75mA max.
45% min, 50% typical, 55% max.
VOH = VDD-2V (VDD-1.025V min)
VOL = VDD-2V (VDD-1.620V max)
0.7ns max, 0.4ns typical
0.7ns max, 0.4ns typical
LVDS
Supply Current (IDD) [Fout = 212.50MHz]
Output Clock Duty Cycle @ 1.25V
Output Differential Voltage (VOD)
VDD Magnitude Change (
∆VOD)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
Ω]
Offset Magnitude Voltage[RL = 100
Ω]
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (tr) [RL=100
Ω, CL=10pF]
Differential Clock Fall Time (tf) [RL=100
Ω, CL=10pF]
CMOS
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]
Output Clock Duty Cycle [Measured @ 50% VDD]
1.6ns max, 1.2ns typical
45% min, 50% typical, 55% max
60mA max, 55mA typical.
45% min, 50% typical, 55% max
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
VOH = 1.6V max, 1.4V typical
VOL = 0.9V min, 1.1V typical
VOS = 1.125V min, 1.1V typical, 1.375V max
∆VOS = 0mV min, 3mV typical, 25mV max
±10
µA max, ±1µA typical
0.2ns min, 0.5ns typical, 0.7ns max
0.2ns min, 0.5ns typical, 0.7ns max
: PRELIMINARY


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