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TDA4856 Datasheet(PDF) 7 Page - NXP Semiconductors |
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TDA4856 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 56 page  1999 Jul 13 7 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Frequency-locked loop The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the recommended maximum ratio is This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included. Without a horizontal sync signal the oscillator will be free-running at fmin. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching. In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor connected between pins HBUF and HREF defines the frequency range. Out-of-lock indication (pin HUNLOCK) Pin HUNLOCK is floating during search mode, or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage. For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output. The continuous protection blanking (see Section “Video clamping/vertical blanking generator”) is also available at this pin. Horizontal unlock blanking can be switched off, by control bit BLKDIS via the I2C-bus while vertical blanking is maintained. Horizontal oscillator The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed. The minimum oscillator frequency is determined by a resistor from HREF to ground. A resistor connected between pins HREF and HBUF defines the frequency range. The reference current at pin HREF also defines the integration time constant of the vertical sync integration. Calculation of line frequency range The oscillator frequencies fmin and fmax must first be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fsync(min) and fsync(max). The oscillator is driven by the currents in RHREF and RHBUF. The following example is a 31.45 to 90 kHz application: Table 1 Calculation of total spread Thus the typical frequency range of the oscillator in this example is: The resistors RHREF and RHBUFpar can be calculated using the following formulae: . The resistor RHBUFpar is calculated as the value of RHREF and RHBUF in parallel. f max f min ---------- 6.5 1 -------- = spread of for fmax for fmin IC ±3% ±5% CHCAP ±2% ±2% RHREF, RHBUF ±2% ±2% Total ±7% ±9% f max f sync max () 1.07 × 96.3 kHz == f min f sync min () 1.09 ----------------------- 28.4 kHz == R HREF 78 kHz k × ×Ω f min 0.0012 f min 2 × + kHz [] ----------------------------------------------------------------- 2.61 k Ω == R HBUFpar 78 kHz k × ×Ω f max 0.0012 f max 2 × + kHz [] -------------------------------------------------------------------- 726 Ω == |
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