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TDA4854 Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA4854 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 60 page  1999 Jul 13 9 Philips Semiconductors Product specification I2C-bus autosync deflection controllers for PC/TV monitors TDA4853; TDA4854 Horizontal oscillator The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF to be connected at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed. The minimum oscillator frequency is determined by a resistor connected between pin HREF and ground. A resistor connected between pins HREF and HBUF defines the frequency range. The reference current at pin HREF also defines the integration time constant of the vertical sync integration. Calculation of line frequency range The oscillator frequencies fmin and fmax must first be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fsync(min) and fsync(max). The oscillator is driven by the currents in RHREF and RHBUF. The following example is a 31.45 to 90 kHz application: Table 1 Calculation of total spread Thus the typical frequency range of the oscillator in this example is: The TV mode is centred around fmin with a control range of ±10%. Activation of the TV mode is only allowed between 15.625 and 35 kHz. The resistors RHREF and RHBUFpar can be calculated using the following formulae: The resistor RHBUFpar is calculated as the value of RHREF and RHBUF in parallel. The formulae for RHBUF also takes into account the voltage swing across this resistor PLL1 phase detector The phase detector is a standard type using switched current sources, which are independent of the horizontal frequency. It compares the middle of the horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26). See also Section “Horizontal position adjustment and corrections”. Horizontal position adjustment and corrections A linear adjustment of the relative phase between the horizontal sync and the oscillator sawtooth (in PLL1 loop) is achieved via register HPOS. Once adjusted, the relative phase remains constant over the whole frequency range. Correction of pin unbalance and parallelogram is achieved by modulating the phase between the oscillator sawtooth and horizontal flyback (in loop PLL2) via registers HPARAL and HPINBAL. If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from the horizontal phase via control bit ACD. This does not change the output at pin ASCOR. Horizontal moire cancellation To achieve a cancellation of horizontal moire (also known as ‘video moire’), the horizontal frequency is divided-by-two to achieve a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half of the vertical frequency. Control bit MOD disables the moire cancellation function. spread of for fmax for fmin IC ±3% ±5% CHCAP ±2% ±2% RHREF, RHBUF ±2% ±2% Total ±7% ±9% f max f sync max () 1.07 × 96.3 kHz == f min f sync min () 1.09 ----------------------- 28.9 kHz == R HREF 78 kHz k × ×Ω f min 0.0012 f min 2 × + kHz [] ----------------------------------------------------------------- 2.61 k Ω == R HBUFpar 78 kHz k × ×Ω f max 0.0012 f max 2 × + kHz [] -------------------------------------------------------------------- 726 Ω == R HBUF R HREF R HBUFpar × R HREF R HBUFpar – ---------------------------------------------- 0.8 × = 805 Ω = |
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