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MH8S72BALD-7 Datasheet(PDF) 18 Page - Mitsubishi Electric Semiconductor |
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MH8S72BALD-7 Datasheet(HTML) 18 Page - Mitsubishi Electric Semiconductor |
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18 / 55 page  MH8S72BALD -7,-8,-10 603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM MITSUBISHI LSIs ( / 55 ) MITSUBISHI ELECTRIC 29.Oct.1998 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0225-0.4 Multi Bank Interleaving WRITE (BL=4) CK Command A10 DQ ACT Xa Xa 00 Write Y 0 00 Write Y 0 10 Da0 Da1 Da2 Da3 ACT Xb Xb 10 PRE 0 00 tRCD Db0 Db1 Db2 Db3 tRCD CK Command A10 DQ ACT Xa Xa 00 Write Y 1 00 Da0 Da1 Da2 Da3 ACT Xa Xa 00 Internal precharge begins tRCD tRP WRITE with Auto-Precharge (BL=4) WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be WRITE command is issued and the remaining burst length is ignored.The read data burst length os unaffected while in this mode. 18 A0-9 BA0,1 A0-9 BA0,1 A11 Xa Xb 0 PRE 0 10 0 A11 Xa Xa tWR |
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