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TDA4850 Datasheet(PDF) 5 Page - NXP Semiconductors |
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TDA4850 Datasheet(HTML) 5 Page - NXP Semiconductors |
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1997 Jun 05 5 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage. Vertical sync separator, polarity correction and vertical sync integrator DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then polarity is corrected. The polarity information is fed to the VGA mode detector. If pin 10 is not used, it must be connected to ground. The separated Vi(sync) signal from pin 10, or the integrated composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator. VGA mode detector and mode output The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from VP to pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters. VGA mode detector input For multi-frequency operation the voltage on pin 7 must be externally forced to a level of <50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 to 300 µs (575 µs is needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 to 110 Hz. Clamping and blanking generator A combined clamping and blanking pulse is available on pin 8 (suitable for the video preamplifier TDA4880). The lower level of 2.1 V can be the blanking signal derived from line flyback, or the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals to the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA as well as for multi-frequency operation (selectable via pin 7). The upper level of 3.9 V is the horizontal clamping pulse with internally fixed pulse width of 1 µs. A mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. PLL1 phase detector The phase detector is a standard one using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17. Horizontal oscillator This oscillator is a relaxation type oscillator. Its frequency is determined mainly by the capacitor on pin 19. A frequency range of one octave is achieved by the current on pin 18. The ϕ1 control voltage from pin 17 is fed via a buffer amplifier and an attenuator to the current reference pin 18 to achieve a high DC loop gain. Therefore, changes in frequency will not affect the phase relationship between horizontal sync pulses and line flyback pulses. PLL2 phase detector This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses. A certain amount of phase adjustments is possible by injecting a DC current from an external source into the PLL2 filter capacitor on pin 20. |
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