QAMI5107 datasheet(3/6 Pages) STMICROELECTRONICS | Low-cost QAM demodulator and MPEG2 decoder SOC for set-top boxes

3 / 6 page

QAMi5107

Description

3/6

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Additional I2C bus (I2C repeater) dedicated to tuner control for minimum tuner

disturbance

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Programmable clock derived from system clock and available for external use

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Parallel and serial output interfaces, with DVB common interface support

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On chip voltage regulator

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CMOS technology, 1.0 V operation

1.2

Decoder features

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Enhanced ST20 32-bit VL-RISC CPU

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200-MHz, single cycle cache, 4-Kbyte instruction cache, 4-Kbyte data cache, 2-Kbyte

SRAM

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Unified memory interface

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Up to 166 MHz,16-bit wide SDRAM interface and 133 MHz DDR interface

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Programmable flash memory interface

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4 separately configurable banks, 8/16-bits wide

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SRAM, peripheral, flash, SFlash™ support

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Support for low cost DVB-CI

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Programmable transport interfaces (PTI)

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single transport stream input

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support for DVB transport streams

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integrated DVB, ICAM descramblers

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MPEG2 MP@ML video decoder

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Fully programmable horizontal and vertical SRCs

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Graphics/display

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3 display planes

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8 bpp CLUT graphics, 256 x 30 bits (AYCbCr) CLUT entries, 16 bpp true color

graphics, RGB565, ARGB1555, ARGB4444 formats. Link list control

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Alpha blending, antialiasing, antiflutter, antiflicker filters

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2-D paced blitter engine with fill function

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Blitter based display compositor

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Digital video output: compliant with CCIR 601/CCIR 656.

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PAL/NTSC/SECAM encoder

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RGB, CVBS, Y/C and YUV outputs with four 10-bit DACs outputs. RGB/CVBS or

YUV/CVBS or YC/CVBS

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Encoding of CGMS, Teletext, WSS, VPS, closed caption

■ Audio subsystem

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MPEG-1 layers I/II decoding

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Simultaneous MPEG audio decode and output of Dolby streams on S/PDIF

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IEC958/IEC1937 digital audio output interface

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Integrated stereo audio DAC system

■ Central DMA controller

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