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QAMI5107 Datasheet(PDF) 2 Page - STMicroelectronics

Part No. QAMI5107
Description  Low-cost QAM demodulator and MPEG2 decoder SOC for set-top boxes
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com

QAMI5107 Datasheet(HTML) 2 Page - STMicroelectronics

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The QAMi5107 provides an integrated demodulator/decoder solution for digital cable
receivers for compressed video, sound and data services. A QAM (quadrature amplitude
modulation) demodulator and FEC performs IF to MPEG-2 block processing of QAM
carriers. The demodulated stream is then processed by video and audio decoders.
The device implements a fully unified SDR SDRAM based memory architecture that
integrates the Omega2 video decoder cell together with a blitter engine and a multichannel
DMA controller to provide enhanced performance for graphics and real-time stream
transfers. Transfer of data such as pixmaps, audio streams, stills and PES can be performed
efficiently using the QAMi5107 DMA.
A true-color mode provides OSD graphics allowing the display of RGB16 formats: RGB565,
ARGB1555 and ARGB4444. This directly supports up to 65,536 colors in a region. Alpha
blending by region or by pixel is available for mixing with video and background layers. The
above feature set, guarantees a smooth user interface and high performance for demanding
middlewares such as MHP™.
The QAMi5107 is the first single chip cable STB IC to combine a very low cost solution with
advanced security features. DVB and ICAM descramblers together with a smart card
interface ensure that all the major conditional access systems can be supported.
QAM Demodulator features
Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
Processes Japanese transport stream multiplex frame (TSMF)
High-performance integrated A/D converter suitable for direct IF architecture in all QAM
(quadrature amplitude modulation) modes
Supports 16, 32, 64, 128 and 256 point constellations
Very low power consumption
Full digital demodulation
Variable symbol rates
Front derotator for better low symbol rate performance and relaxed tuner constraints
Integrated matched filtering
Robust integrated adaptive pre and post equalizer
On-chip FEC A/C with ability to bypass individual blocks
10 programmable GPIO
Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
Integrated signal quality monitors, plus lock indicator and interrupt function mapped to
GPIO pin
Improved signal acquisition
System clock generated on-chip from quartz crystal
Low frequency crystal operations 4, 16, 25 - 30 MHz
4 I²C addresses
Easy control and monitoring via 2-wire fast I2C bus

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