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A25L40P Datasheet(PDF) 23 Page - AMIC Technology |
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A25L40P Datasheet(HTML) 23 Page - AMIC Technology |
23 / 38 page A25L40P Series PRELIMINARY (May, 2007, Version 0.4) 22 AMIC Technology Corp. Figure 18. Release from Deep Power-down (RES) Instruction Sequence S C D 1 2 3 45 6 7 0 Instruction t RES1 High Impedance Q Stand-by Mode Deep Power-down Mode Driving Chip Select ( S ) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 18.), still insures that the device is put into Stand-by Power mode. If the device was not pre- viously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select ( S ) must remain High for at least tRES1 (max), as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. |
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