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PIC18F4520 Datasheet(PDF) 6 Page - Microchip Technology |
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PIC18F4520 Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 16 page  PIC18F2420/2520/4420/4520 DS80209D-page 6 © 2005 Microchip Technology Inc. 19. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), the second byte may be corrupted if it is written into TXREG immediately after the TMRT bit is set. Work around Execute a software delay, at least one-half the transmission’s bit time, after TMRT is set and prior to writing subsequent bytes into TXREG. Date Codes that pertain to this issue: All engineering and production devices. 20. Module: Timer1/Timer3 When Timer1 or Timer3 is configured for external clock source, and the CCPxCON register is configured with 0x0B (Compare mode, trigger special event), the timer is not reset on a Special Event Trigger. Work around Modify firmware to reset the Timer1/Timer3 registers upon detection of the compare match condition — TMRxL and TMRxH. Date Codes that pertain to this issue: All engineering and production devices. 21. Module: Timer1/Timer3 When Timer1 or Timer3 is in External Clock Synchronized mode and the external clock period is between 1 and 2 TCY, interrupts will occasionally be skipped. Work around Avoid using an external clock with a period (1/ frequency) between 1 and 2 TCY. Date Codes that pertain to this issue: All engineering and production devices. 22. Module: Timer1/Timer3 When Timer1/Timer3 is operating in 16-bit mode and the prescale setting is not 1:1, a write to the TMR1H/TMR3H Buffer registers may lengthen the duration of the period between the increments of the timer for the period in which TMR1H/TMR3H was written. Work around Two work arounds are available: 1) Stop Timer1/ Timer3 before writing the TMR1H/TMR3H registers; 2) Write TMR1L/TMR3L immediately after writing TMR1H/TMR3H. Date Codes that pertain to this issue: All engineering and production devices. |
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