Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF HTML

PIC18F2420 Datasheet(PDF) 2 Page - Microchip Technology

Part No. PIC18F2420
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com

PIC18F2420 Datasheet(HTML) 2 Page - Microchip Technology

Zoom Inzoom in Zoom Outzoom out
 2 / 16 page
background image
DS80209D-page 2
© 2005 Microchip Technology Inc.
Module: MSSP
When the MSSP is configured for SPI™ Master
mode, the SDO pin cannot be disabled by setting
the TRISC<5> bit. The SDO pin always outputs
the content of SSPBUF regardless of the state of
the TRIS bit.
In Slave mode with Slave Select enabled,
SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the
SDO pin can be disabled by placing a logic high
level on the SS pin (RA5).
Work around
Date Codes that pertain to this issue:
All engineering and production devices.
Module: MSSP
After an I2C transfer is initiated, the SSPBUF
register may be written for up to 10 TCY before
additional writes are blocked. The data transfer may
be corrupted if SSPBUF is written during this time.
The WCOL bit is set any time an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
Module: MSSP
In 10-bit Addressing mode, when a Repeated Start
is issued, followed by the high address byte and a
write command (R/W = 0), an ACK is not issued.
Work around
There are two work arounds available:
1. Single-Master Environment:
In a single-master environment, the user must
issue a Stop, then a Start, followed by a write
to the address high, then the address low
followed by the data.
2. Multi-Master Environment:
In a multi-master environment, the user must
issue a Repeated Start, send a dummy write
command to a different address, issue another
Repeated Start and then send a write to the
original address. This procedure will help
maintain control of the bus.
Date Codes that pertain to this issue:
All engineering and production devices.
Module: MSSP
I2C Receive mode should be enabled (i.e., RCEN
bit should be set) only when the system is idle
(i.e., when ACKEN, RCEN, PEN, RSEN and SEN
all equal zero). It should not be possible to set the
RCEN bit when the system is not idle, however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become idle before setting the
RCEN bit. This requires a check for the following bits
to be clear:
Date Codes that pertain to this issue:
All engineering and production devices.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 

Datasheet Download

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn