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EPR-00010 Datasheet(PDF) 5 Page - Power Integrations, Inc.

Part No. EPR-00010
Description  15W, Universal Input, Single Output, Isolated Converter with TOP233Y
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Maker  POWERINT [Power Integrations, Inc.]
Homepage  http://www.powerint.com

EPR-00010 Datasheet(HTML) 5 Page - Power Integrations, Inc.

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Engineering Prototype Report
Page 5 of 24
4.0 Circuit Description
Specific features of this circuit (page 4) are:
settable under voltage/over voltage protection, extended input voltage range(85-300Vac), settable
battery charging current limit and charging voltage with correction for battery temperature.
The AC input is rectified (D1-D4) and filtered (C1) to create a high voltage DC buss which is connected
to T1-1. The primary current is modulated by U1 (TOP233Y) at 130kHz(U1-4 connected to U1-3). The
secondary induced voltage(T-7,8) is rectified and filtered by D7, C4 with additional filtering provided by
L2, C5 to give the 14Vdc output.
The input fuse F1 is sized to resist the capacitor C1 charging current and isolates the line from a
potential rectifier bridge (D1-D4) failure. Inductor L1 reduces the common mode noise and its leakage
inductance together with CX1, the differential mode noise. The frequency jitter in TOP233Y (U1) allows
the unit to meet worldwide conducted EMI standards using a common mode choke (L1) in combination
with small value capacitors (CX1and CY1) and a proper PCB layout. The input filter is optimized when
the EMI requirements are met with the lowest L1 (leak)*CX1 product value. Resistors R1+ R2 value
(1.91Mohm) sets the under voltage (UVLO) and the overvoltage (OVLO) lock out voltage levels.
The TOP233Y (U1-2) UV/OV threshold currents are 50/225uA, with 10uA hysteresis, going down, for
225uA (215uA threshold). UVLO= 50uA* 1.91Mohm= 95.5 Vdc (~75Vac), OVLO=225uA* 1.91Mohm=
430Vdc (~307Vac). On the rising input voltage, turn ON occurs at > 50uA (UVLO=95.5Vdc) and turn
OFF at >225uA (OVLO=430Vdc). On the falling input voltage, turn ON occurs < 215uA (OVLO= 411Vdc)
and turn OFF at <50uA and loss of regulation. The power supply turns off automatically when it loses the
regulation at a given output load. VR1 and D5 form a clamp circuit that limits the turn-off voltage spike to
a safe level on U1-5 (DRAIN) pin.
There are two output control loops, both feeding back into the control pin (U1-1). The current input is
supplied by the bias winding (T1-3,4) and modulated by the optocoupler (U2-3,4) phototransistor. The
optocoupler (U2-1,2) photodiode current is controlled by:
1- The voltage control loop (U3, R7, R9,10, 11, RT1) in the constant voltage mode.
2- The current control loop (Q1, R4,5,6) in the constant current mode.
1.The 14Vdc output voltage is controlled by the sum of the voltage drops across the opto-coupler U2 and
the voltage regulator U3. Resistor R8 (AC gain of the circuit) limits the current through U2, improving its
response time. Resistor R7 sets the bias current for and C7 provides compensation for U3.
Different output voltages can be selected by changing R9, R10, R11 and RT1 according to this formula:
Vout= 2.5Vdc(1+(R11+(R10*RT1/R10+RT1))/R9), R10=11.5k 1%
If RT1 is not used:
Vout= 2.5Vdc(1+(R11+R10)/R9), R10 must be 11.5k/2
(install a 11.5k 1% in parallel with existing R10).
2.The output current is limited to Iout~ 1.2A=0.6V/0.5ohm(Q1 Vce(sat)/R4, R5 parallel resistance).
The accuracy of Iout is limited by the Vce variation with the temperature and the precision of the
current shunt R4, R5.
The primary-to-secondary isolation is provided by using parts/materials (opto/transformer insulation) with
the correct level of isolation and creepage distances (opto slot/transformer bobbin). Also the CY1 value
(while allowing common mode noise current path) has to keep the leakage current below the standard
(IEC950) accepted value.
The 14Vdc monitoring light emitting diode (LED1) and 6.8k R12 are optional, and have been included in
this circuit for troubleshooting convenience.

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