7

This is a developmental specification and is subject to change without notice.

N256S0818HDA/N256S0830HDA

AMI Semiconductor, Inc.

Advance Information

READ Operations

The serial SRAM READ is selected by enabling CS low. First, the 8-bit READ instruction is transmitted to

the device followed by the 16-bit address with the MSB being a don’t care. After the READ instruction and

addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output

valid time from the clock edge.

If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory

location on the page can be read sequentially by continuing to provide clock pulses. The internal address

pointer is automatically incremented to the next higher address on the page after each word of data is read

out. This can be continued for the entire page length of 32 words long. At the end of the page, the

addresses pointer will be wrapped to the 0 word address within the page and the operation can be

continuously looped over the 32 words of the same page.

If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory

location can be read sequentially by continuing to provide clock pulses. The internal address pointer is

automatically incremented to the next higher address after each word of data is read out. This can be

continued for the entire array and when the highest address is reached (7FFFh), the address counter

wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely.

All READ operations are terminated by pulling CS high.

Word READ Sequence

CS

Instruction

SI

04

3

25

16

9

810

7

11

SCK

15

14

13

12

210

7

6543

210

High-Z

16-bit address

Data Out

SO

21

23

22

24

28

29

30

31

26

27

25

000

0

0

011