FS7140-01 datasheet(13/15 Pages) AMI

Part #	FS7140-01

Description	Programmable Phase-Locked Loop Clock Generator

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AMI Semiconductor - Rev. 3.0

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FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet

Table 13: AC Timing Specifications

Parameter

Symbol

Conditions/Description

Clock

(MHz)

Min.

Typ.

Max.

Units

Overall

Output Frequency*

fO(max)

CMOS outputs

0

150

MHz

PECL outputs

0

300

VCO Frequency*

fVCO

40

400

MHz

CMOS Mode Rise Time*

tr

CL = 7pF

1ns

CMOS Mode Fall Time*

tf

CL = 7pF

1

ns

PECL Mode Rise Time*

tr

CL = 7pF; RL = 65 ohm

1ns

PECL Mode Fall Time*

tf

CL = 7pF; RL = 65 ohm

1

ns

Reference Frequency Input (REF)

Input Frequency

FREF

80

MHz

Reference High Time

tREHF

3

ns

Reference Low Time

tREFL

3ns

Sync Control Input (SYNC)

Sync High Time

tSYNCH

for orderly CLK stop/start

3

TCLK

Sync Low Time

tSYNCL

for orderly CLK stop/start

3

TCLK

Clock Output (CLKP, CLKN)

Duty Cycle (CMOS Mode)*

Measured at 1.4V

50

%

Duty Cycle (PECL Mode)*

Measured at zero crossings of (VCLKP-VCLKN)

50

%

Jitter, Long Term (

sg(t))*

tj(LT)

For valid programming solutions. Long-term (or cumulative) jitter specified is RMS

position error of any edge compared with an ideal clock generated from the same

reference frequency. It is measured with a time interval analyzer using a 500

microsecond window, using statistics gathered over 1000 samples.

ps

FREF/NREF > 1000kHz

25

ps

FREF/NREF ~= 500kHz

50

ps

FREF/NREF ~= 250kHz

100

ps

FREF/NREF ~= 125kHz

190

ps

FREF/NREF ~= 62.5kHz

240

ps

FREF/NREF ~= 31.5kHz

300

ps

Jitter, Period (peak-peak)*

tj(DP)

40MHz < VCO Frequency < 100MHz

75

ps

VCO Frequency > 100MHz

50

ps

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. MIN and MAX characterization data are ± 3

s from typical.

Table 14: Serial Interface Timing Specifications

Parameter

Symbol

Conditions/Description

Fast Mode

Units

Min.

Max.

Clock Frequency

fSCL

SCL

0

400

kHz

Bus Free Time Between STOP and START

tBUF

1300

ns

Setup Time, START (repeated)

tsu:STA

600

ns

Hold Time, START

thd:STA

600

ns

Setup Time, Data Input

tsu:DAT

SDA

100

ns

Hold Time, Data Input

thd:DAT

SDA

0

ns

Output Data Valid From Clock

tAA

900

ns

Rise Time, Data and Clock

tR

SDA, SCL

300

ns

Fall Time, Data and Clock

tF

SDA, SCL

300

ns

High Time, Clock

tHI

SCL

600

ns

Low Time, Clock

tLO

SCL

1300

ns

Setupt Time, STOP

tsu:STO

600

ns

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. MIN and MAX characterization data are ± 3

s from typical.

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