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FS7140-01 Datasheet(PDF) 5 Page - AMI SEMICONDUCTOR

Part # FS7140-01
Description  Programmable Phase-Locked Loop Clock Generator
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Manufacturer  AMI [AMI SEMICONDUCTOR]
Direct Link  http://www.amis.com
Logo AMI - AMI SEMICONDUCTOR

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AMI Semiconductor - Rev. 3.0
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FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet
5.2 I2C-bus Operation
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is
not busy. During the data transfer, the data line (SDA) must
remain stable whenever the clock line (SCL) is high. Changes
in the data line while the clock line is high will be interpreted by
the device as a START or STOP condition. The following bus
conditions are defined by the I2C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL input is
high indicates a START condition. All commands to the device
must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high
indicates a STOP condition. All commands to the device must
be followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line
is stable for the duration of the high period of the SCL line after
a START condition occurs. The data on the SDA line must be
changed only during the low period of the SCL signal. There is
one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is
determined by the master device, and can continue indefinitely.
However, data that is overwritten to the device after the first
eight bytes will overflow into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate
an acknowledge after each byte is received. The master device
must generate an extra clock pulse to coincide with the
acknowledge bit. The acknowledging device must pull the SDA
line low during the high period of the master acknowledge
clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has been
read (clocked) out of the slave. In this case, the slave must
leave the SDA line high to enable the master to generate a
STOP condition.
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface. The
crystal oscillator does not have to run for communication to
occur.
The device accepts the following I2C-bus commands:
5.2.1 Slave Address
After generating a START condition, the bus master broadcasts
a seven-bit slave address followed by a R/W bit. The address
of the device is:
where X is controlled by the logic level at the ADDR pins. The
selectable ADDR bits allow four different FS7140 devices to
exist on the same bus. Note that every device on an I2C-bus
must have a unique address to avoid pos-sible bus conflicts.
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
0
X
X
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to
any register. To initiate a write procedure, the R/W bit that is
transmitted after the seven-bit device address is a logic-low.
This indicates to the addressed slave device that a register
address will follow after the slave device acknowledges its
device address. The register address is written into the slave's
address pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the addressed
register. A final acknowledge is returned by the device, and the
master generates a STOP condition.
If either a STOP or a repeated START condition occurs during
a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from
any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the
register write procedure. This indicates to the addressed slave
device that a register address will follow after the slave device
acknowledges its device address. The register address is then
written into the slave's address pointer.
Following an acknowledge by the slave, the master generates
a repeated START condition. The repeated START terminates
the write procedure, but not until after the slave's address
pointer is set. The slave address is then resent, with the R/W
bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address,
and then transmits the eight-bit word. The master does not


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