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FS714001 Datasheet(PDF) 3 Page  AMI SEMICONDUCTOR 

FS714001 Datasheet(HTML) 3 Page  AMI SEMICONDUCTOR 
3 / 15 page 3 AMI Semiconductor  Rev. 3.0 www.amis.com FS714001 / FS714001g / FS7145 Programmable PhaseLocked Loop Clock Generator Data Sheet R REF F VCO N f N f = This basic PLL equation can be rewritten as ÷÷ ø ö çç è æ = R F REF VCO N N f f A postdivider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is: ÷÷ ø ö çç è æ ÷÷ ø ö çç è æ = Px R F REF CLK N N N f f 1 Post Divider 1 (N P1 ) Post Divider 2 (N P2) Post Divider 3 (N P3) POST3[1:0] POST2[3:0] POST1[3:0] POST DIVIDER (N Px) f CLK f VCO Figure 3: Post Divider The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPx. 3 2 1 P P P Px N N N N ´ ´ = 4.0 Functional Block Description 4.1 Phase Locked Loop (PLL) The phase locked loop is a standard phase and frequency locked loop architecture. The PLL consists of a reference divider, a phasefrequency detector (PFD), a charge pump, an internal loop filter, a voltagecontrolled oscillator (VCO), a feedback divider, and a post divider. The reference frequency (generated by either the onboard crystal oscillator or an external frequency source), is first reduced by the Reference Divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then: 4.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider is a 12 bit divider, and can be programmed for any modulus from 1 to 4095 (divide by 1 not available on date codes prior to 0108). 4.1.2 Feedback Divider The feedback divider is based on a dualmodulus divider (also called dualmodulus prescaler) technique. It permits division by any integer value between 12 and 16383. Simply program the FBKDIV register with the binary equivalent of the desired modulus. Selected moduli below 12 are also permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not available on date codes prior to 0108). 4.1.3 Post Divider The post divider consists of three individually programmable dividers, as shown in Figure 3. The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). See Table 8 for additional information. 4.1.4 Crystal Oscillator The FS7140 is equipped with a Piercetype crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, crystals for other standard load capacitances may be used if great precision of the reference frequency (100ppm or less) is not required. 4.1.5 Reference Divider Source MUX The source of frequency for the reference divider can be chosen to be the device crystal oscillator or the REF pin by the REFDSRC bit. When not using the crystal oscillator, it is preferred to connect 
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