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LTC4215IGN Datasheet(PDF) 7 Page - Linear Technology |
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LTC4215IGN Datasheet(HTML) 7 Page - Linear Technology |
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7 / 24 page  LTC4215 7 4215fb TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error vs Code (ADIN) ADC INL vs Code (ADIN) CODE 0 64 128 192 0 0.001 0.002 0.003 0.004 0.006 4215 G13 256 0.005 CODE 0 128 192 4215 G14 256 64 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 ADC DNL vs Code (ADIN) ADC Full-Scale Error vs Temperature TEMPERATURE ( °C) –50 –25 –1.0 –0.2 1.0 0 50 4215 G05 –0.6 0.6 0.2 –0.4 0.8 –0.8 0.4 0 25 75 100 TA = 25°C, VDD = 12V unless otherwise noted CODE 0 –0.5 –0.4 –0.3 –0.1 –0.2 0 0.1 0.2 0.5 0.4 128 4215 G15 256 64 192 0.3 PI FU CTIO S ADIN (QFN Package): ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1, ADR2 (ADR1, ADR2 Available in QFN Pack- age): Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or open configures one of 27 possible addresses. See Table 1 in Applications Information. ⎯A⎯L⎯E⎯R⎯T: Fault Alert Output. Open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ⎯A⎯L⎯E⎯R⎯T register. See Applications Information. Tie to ground if unused. ⎯E⎯N: (QFN package) Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10µA current source pulls up this pin. Transitions on this pin are recorded in the Fault register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information. |
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