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SN74SSTU32866 Datasheet(PDF) 19 Page - Texas Instruments |
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SN74SSTU32866 Datasheet(HTML) 19 Page - Texas Instruments |
19 / 37 page SN74SSTU32866 25BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESSPARITY TEST SCES564 − APRIL 2004 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). C. tPLH and tPHL are the same as tpd. Output Waveform 1 VOL tPHL VCC VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (HIGH-TO-LOW) Timing Inputs VICR VICR VCC/2 LOAD CIRCUIT VCC CL = 10 pF (see Note A) Test Point DUT Out RL = 1 kΩ 0.15 V Output Waveform 2 VOH tPLH 0 V 0 V VCC VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (LOW-TO-HIGH) LVCMOS RESET Input VCC/2 VI(PP) Output Waveform 2 0 V tPHL VOH VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (LOW-TO-HIGH) Timing Inputs VICR VICR VI(PP) 0.15 V Figure 3. Error Output Load Circuit and Voltage Waveforms |
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