SN74SSTU32866

25BIT CONFIGURABLE REGISTERED BUFFER

WITH ADDRESSPARITY TEST

SCES564 − APRIL 2004

28

POST OFFICE BOX 655303

timing diagram for the first SN74SSTU32866 (1:2 Register-A configuration) device used in pair;

C0 = 0, C1 = 1 (RESET switches from H to L)

CLK†

D1−D14†

RESET

DCS†

CSR†

CLK†

Q1−Q14

PAR_IN†

PPO

QERR

(not used)

tinact

tRPHL

RESET to Q

tRPHL

RESET to PPO

tRPLH

RESET to QERR

H, L, or X

H or L

† After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum

time of tinact max.