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LTC3718 Datasheet(PDF) 1 Page - Linear Technology |
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LTC3718 Datasheet(HTML) 1 Page - Linear Technology |
1 / 20 page 1 LTC3718 3718fa FEATURES APPLICATIO S DESCRIPTIO TYPICAL APPLICATIO Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination s Very Low VIN(MIN): 1.5V s Ultrafast Transient Response s True Current Mode Control s 5V Drive for N-Channel MOSFETs Eliminates Auxillary 5V Supply s No Sense Resistor Required s Uses Standard 5V Logic-Level N-Channel MOSFETs s VOUT(MIN): 0.4V s VOUT Tracks 1/2 VIN or External VREF s Symmetrical Source and Sink Output Current Limit s Adjustable Switching Frequency s tON(MIN) <100ns s Power Good Output Voltage Monitor s Programmable Soft-Start s Output Overvoltage Protection s Optional Short-Circuit Shutdown Timer s Small 24-Lead SSOP Package s Bus Termination: DDR/QDR Memory, SSTL, HSTL, ... s Servers, RAID Systems s Distributed Power Systems s Synchronous Buck with General Purpose Boost The LTC ®3718 is a high current, high efficiency synchro- nous switching regulator controller for DDR and QDR TM memory termination. It operates from an input as low as 1.5V and provides a regulated output voltage equal to (0.5)VIN. The controller uses a valley current control architecture to enable high frequency operation with very low on-times without requiring a sense resistor. Operating frequency is selected by an external resistor and is com- pensated for variations in VIN and VOUT. The LTC3718 uses a pair of standard 5V logic level N-channel external MOSFETs, eliminating the need for expensive P-channel or low threshold devices. Forced continuous operation reduces noise and RF inter- ference. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an optional short-circuit timer. Soft-start capability for sup- ply sequencing can be accomplished using an external timing capacitor. OPTI-LOOP ® compensation allows the transient response to be optimized over a wide range of loads and output capacitors. Efficiency vs Load Current , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc. CSS 0.1 µF RC 4.75k LTC3718 C1 820pF X7R RON 237k RF1 12.1k COUT: SANYO POSCAP 4TPB470M L1: SUMIDA CEP125-0R8MC L2: PANASONIC ELJPC4R7MF RF2 37.4k CIN2 4.7 µF L2 4.7 µH M2 Si7440DP D2 B340A 3718 TA01 L1 0.8 µH D3 MBR0520 CVCC1 10 µF CB 0.33 µF DB CMDSH-3 COUT 470 µF ×2 M1 Si7440DP VIN 2.5V VOUT 1.25V ±10A VIN CIN1 22 µF ×2 D1 B340A SHDN BOOST VREF TG ION SW1 VFB1 SENSE+ PGOOD PGND1 RUN/SS SENSE– ITH BG SGND1 INTVCC SGND2 VIN1 VFB2 SW2 PGND2 VIN2 VOUT + Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply LOAD CURRENT (A) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 100 3718 G05/TA01a 0.1 VIN = 2.5V VOUT = 1.25V FIGURE 1 CIRCUIT |
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