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SN74LVC2G74-Q1 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN74LVC2G74-Q1
Description  SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74LVC2G74-Q1 Datasheet(HTML) 1 Page - Texas Instruments

 
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FEATURES
DCUPACKAGE
(TOP VIEW)
3
6
CLR
Q
8
1
V
CC
CLK
5
GND
4
Q
2
7
PRE
D
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G74-Q1
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES563B – MARCH 2004 – REVISED AUGUST 2006
Qualification in Accordance With
Latch-Up Performance Exceeds 100 mA Per
AEC-Q100 (1)
JESD 78, Class II
Qualified for Automotive Applications
ESD Protection Exceeds JESD 22
Customer-Specific Configuration Control Can
– 2000-V Human-Body Model (A114-A)
Be Supported Along With Major-Change
– 200-V Machine Model (A115-A)
Approval
– 1000-V Charged-Device Model (C101)
Supports 5-V V
CC Operation
Inputs Accept Voltages to 5.5 V
Max t
pd of 6.9 ns at 3.3 V
Low Power Consumption, 10-
µA Max I
CC
±24-mA Output Drive at 3.3 V
Typical V
OLP (Output Ground Bounce) <0.8 V
at V
CC = 3.3 V, TA = 25°C
Typical V
OHV (Output VOH Undershoot) >2 V at
V
CC = 3.3 V, TA = 25°C
I
off Supports Partial-Power-Down Mode
Operation
(1)
Contact factory for details. Q100 qualification data available
on request.
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
–40
°C to 125°C
VSSOP – DCU
Reel of 3000
SN74LVC2G74QDCURQ1
C74_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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