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SN74ACT7201LA50NP Datasheet(PDF) 8 Page - Texas Instruments |
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SN74ACT7201LA50NP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 23 page SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FIGURE ′ACT7200L-15 ′ACT7201LA-15 ′ACT7202LA-15 ′ACT7200L-25 ′ACT7201LA-25 ′ACT7202LA-25 ′ACT7201LA-35† ′ACT7202LA-35† ′ACT7200L-50 ′ACT7201LA-50 ′ACT7202LA-50 UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency, R or W 40 28.5 22.2 15 MHz tc(R) Cycle time, read 1(a) 25 35 45 65 ns tc(W) Cycle time, write 1(b) 25 35 45 65 ns tc(RS) Cycle time, reset 7 25 35 45 65 ns tc(RT) Cycle time, retransmit 4 25 35 45 65 ns tw(RL) Pulse duration, R low 1(a) 15 25 35 50 ns tw(WL) Pulse duration, W low 1(b) 15 25 35 50 ns tw(RH) Pulse duration, R high 1(a) 10 10 10 15 ns tw(WH) Pulse duration, W high 1(b) 10 10 10 15 ns tw(RT) Pulse duration, FL/RT low 4 15 25 35 50 ns tw(RS) Pulse duration, RS low 7 15 25 35 50 ns tw(XIL) Pulse duration, XI low 10 15 25 35 50 ns tw(XIH) Pulse duration, XI high 10 10 10 10 10 ns tsu(D) Setup time, data before W ↑ 1(b), 6 11 15 18 30 ns tsu(RT) Setup time, R and W high before FL/RT ↑‡ 4 15 25 35 50 ns tsu(RS) Setup time, R and W high before RS ↑‡ 7 15 25 35 50 ns tsu(XI-R) Setup time, XI low before R ↓ 10 10 10 10 15 ns tsu(XI-W) Setup time, XI low before W ↓ 10 10 10 10 15 ns th(D) Hold time, data after W ↑ 1(b), 6 0 0 0 5 ns th(E-R) Hold time, R low after EF ↑ 5, 11 15 25 35 50 ns th(F-W) Hold time, W low after FF ↑ 6, 12 15 25 35 50 ns th(RT) Hold time, R and W high after FL/RT ↑ 4 10 10 10 15 ns th(RS) Hold time, R and W high after RS ↑ 7 10 10 10 15 ns † Released in RJ package only ‡ These values are characterized but not currently tested. |
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