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PLL602-30 Datasheet(PDF) 1 Page - PhaseLink Corporation

Part No. PLL602-30
Description  750kHz - 800MHz Low Phase Noise XO (for 12 - 25MHz Crystals)
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
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PLL602-30 Datasheet(HTML) 1 Page - PhaseLink Corporation

   
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PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
FEATURES
• 750kHz to 800MHz output range.
• Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -123dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
115dBc/Hz for 622.08MHz).
• Selectable CMOS, PECL and LVDS output.
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• 12MHz to 25MHz crystal input.
• Output Enable selector.
• 3.3V operation.
• Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL602-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) XO IC
Die, with selectable CMOS, LVDS or PECL output,
covering the 750kHz to 800MHz output range, using
a low frequency crystal.
This makes the PLL602-30 ideal as a universal die
for applications ranging from low frequency to
SONET.
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
BLOCK DIAGRAM
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
Selected Output
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
PECL
1
1
LVDS
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0 (Default)
Output enabled
0
1
Tri-state
0
Tri-state
1 (Default)
1 (Default)
Output enabled
Pad #9:
Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
Reference
Divider
Phase
Detector
Charge
Pump
Loop
Filter
VCO
VCO
Divider
XTAL
OSC
CLKBAR
OE
XIN
XOUT
CLK
+
SEL
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
65 mil
24
22
17
16
15
14
12
11
9
8
6
12345
27
28
30
OE_SEL^
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
XIN
XOUT
SEL2
SEL3
OE_CTRL
N/C
Die ID:
A1414-14E
C502A


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